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IDT74ALVCHR16601 Datasheet(PDF) 5 Page - Integrated Device Technology

Part No. IDT74ALVCHR16601
Description  3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS AND BUS-HOLD
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT74ALVCHR16601 Datasheet(HTML) 5 Page - Integrated Device Technology

   
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INDUSTRIALTEMPERATURERANGE
IDT74ALVCHR16601
3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVERWITH3-STATEOUTPUTS
5
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
SWITCHING CHARACTERISTICS(1)
VCC = 2.5V ± 0.2V
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fMAX
150
150
150
MHz
tPLH
PropagationDelay
1
4.8
5.1
1
4.4
ns
tPHL
Ax to Bx or Bx to Ax
tPLH
PropagationDelay
1
5.5
5.8
1
5.1
ns
tPHL
LEAB to Bx or LEBA to Ax
tPLH
PropagationDelay
1.2
5.9
6.3
1.4
5.4
ns
tPHL
CLKAB to Bx or CLKBA to Ax
tPZH
OutputEnableTime
1.1
6.3
6.6
1.1
5.6
ns
tPZL
OEAB to Bx or OEBA to Ax
tPZH
OutputDisableTime
1
4.2
5.1
1.6
4.7
ns
tPZL
OEAB to Bx or OEBA to Ax
tSU
Set-upTime,databeforeCLK
2.3
2.4
2.1
ns
tSU
Set-up Time, data before LE
↓, CLK HIGH
2
1.6
1.6
ns
tSU
Set-up Time, data before LE
↓, CLK LOW
1.3
1.2
1.1
ns
tSU
Set-up Time, CLKEN before CLK
2
2
1.7
ns
tH
Hold Time, data after CLK
0.7
0.7
0.8
ns
tH
Hold Time, data after LE
↓, CLK HIGH
1.3
1.6
1.4
ns
tH
Hold Time, data after LE
↓, CLK LOW
1.7
2
1.7
ns
tH
Hold Time, CLKEN after CLK
0.3
0.5
0.6
ns
tW
Pulse Width, LE HIGH
3.3
3.3
3.3
ns
tW
Pulse Width, CLK HIGH or LOW
3.3
3.3
3.3
ns
tSK(O)
OutputSkew(2)
——
500
ps


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