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IDT74ALVCHR16601 Datasheet(PDF) 2 Page - Integrated Device Technology

Part No. IDT74ALVCHR16601
Description  3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS AND BUS-HOLD
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT74ALVCHR16601 Datasheet(HTML) 2 Page - Integrated Device Technology

   
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INDUSTRIALTEMPERATURERANGE
2
IDT74ALVCHR16601
3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVERWITH3-STATEOUTPUTS
OEAB
A1
GND
A2
A3
VCC
A4
A5
GND
A6
A7
A8
A9
A11
A12
GND
A13
A14
A15
VCC
A16
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
48
49
50
51
52
53
54
55
56
1
CLKENAB
B1
GND
B2
B3
VCC
B4
B5
B6
B7
B8
B9
GND
B11
B12
B13
B14
GND
B15
B16
B17
GND
A18
OEBA
LEBA
25
26
27
28
32
31
30
29
GND
B18
CLKBA
CLKENBA
A10
A17
VCC
B10
LEAB
CLKAB
TSSOP
TOP VIEW
PIN CONFIGURATION
NOTE:
1. As applicable to the device type.
Symbol
Parameter(1)
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
5
7
pF
COUT
Output Capacitance
VOUT = 0V
7
9
pF
CI/O
I/O Port Capacitance
VIN = 0V
7
9
pF
Symbol
Description
Max
Unit
VTERM(2) Terminal Voltage with Respect to GND
–0.5 to +4.6
V
VTERM(3) Terminal Voltage with Respect to GND
–0.5 to VCC+0.5
V
TSTG
Storage Temperature
–65 to +150
°C
IOUT
DC Output Current
–50 to +50
mA
IIK
Continuous Clamp Current,
±50
mA
VI < 0 or VI > VCC
IOK
Continuous Clamp Current, VO < 0
–50
mA
ICC
Continuous Current through each
±100
mA
ISS
VCC or GND
ABSOLUTE MAXIMUM RATINGS(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.
CAPACITANCE (TA= +25°C, F = 1.0MHz)
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
NOTES:
1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA,
CLKBA, and CLKENBA.
2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑ = LOW-to-HIGH transition
3. Output level before the indicated steady-state input conditions were established.
FUNCTION TABLE(1,2)
Inputs
Outputs
CLKENAB
OEAB
LEAB
CLKAB
Ax
Bx
XH
X
X
X
Z
XL
H
X
L
L
XL
H
X
H
H
HL
L
X
X
B(3)
LL
L
LL
LL
L
HH
L
L
L
L or H
X
B(3)
PIN DESCRIPTION
Pin Names
Description
OEAB
A-to-B Output Enable Input (Active LOW)
OEBA
B-to-A Output Enable Input (Active LOW)
LEAB
A-to-BLatchEnableInput
LEBA
B-to-ALatchEnableInput
CLKAB
A-to-B Clock Input
CLKBA
B-to-A Clock Input
A x
A-to-BDataInputsorB-to-A3-StateOutputs(1)
B x
B-to-ADataInputsorA-to-B3-StateOutputs(1)
CLKENAB
A-to-B Clock Enable Input (Active LOW)
CLKENBA
B-to-A Clock Enable Input (Active LOW)


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