 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
IDT74ALVCH16901 Datasheet(PDF) 1 Page - Integrated Device Technology |
|
||||||||||||||||||||||||||||||
IDT74ALVCH16901 Datasheet(HTML) 1 Page - Integrated Device Technology |
|
|
1 / 9 page 
INDUSTRIALTEMPERATURERANGE IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY 1 JUNE 2000 INDUSTRIAL TEMPERATURE RANGE The IDT logo is a registered trademark of Integrated Device Technology, Inc. ©2000 Integrated Device Technology, Inc. DSC-4582/1 FEATURES: • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) •VCC = 3.3V ± 0.3V, Normal Range •VCC = 2.7V to 3.6V, Extended Range •VCC = 2.5V ± 0.2V • CMOS power levels (0.4 µµµµµ W typ. static) • Rail-to-Rail output swing for increased noise margin • Available in TSSOP package FUNCTIONAL BLOCK DIAGRAM APPLICATIONS: • 3.3V high speed systems • 3.3V and lower voltage computing systems DRIVE FEATURES: • High Output Drivers: ±24mA • Suitable for heavy loads IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/ CHECKERS AND BUS-HOLD DESCRIPTION: This 18-bit universal bus transceiver is built using advanced dual metal CMOS technology. The ALVCH16901 is a dual 9-bit to dual 9-bit parity transceiver with registers. The device can operate as a feed-through transceiver or it can generate/check parity from the two 8-bit data buses in either direction. The ALVCH16901 features independent clock (CLKAB or CLKBA), latch-enable (LEAB or LEBA), and dual 9-bit clock enable (CLKENAB or CLKENBA) inputs. It also provides parity-enable (SEL) and parity-select (ODD/EVEN) inputs and separate error-signal (ERRA and ERRB) outputs for checking parity. The direction of data flow is controlled by OEAB and OEBA. When SELislow,theparityfunctionsareenabled. When SELishigh, the parity functions are disabled and the device acts as an 18-bit registered transceiver. The ALVCH16901 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The ALVCH16901 has “bus-hold” which retains the inputs’ last state whenever the input bus goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors. 1 C LKEN A B 2 CLKENAB LE AB OEAB OD D /EV EN 1 A1-1A8 SE L B-Port Parity G enerate and Check A D ata 2 A-Port Parity Generate and Check B Data 18-Bit Storage CLKA B 1 APA R 1 ERRB 2 A1-2A8 2 APAR 2 ERRB 1 B1-1B8 1 BP AR 1 ERRA 2 B1-2A8 2 BP AR 2 ERRA O EBA CLKB A 1 CLKE NB A 2 CLKE NB A LEB A 18-B it S torage 18 18 18 18 QA Q B 2 2 1 32 3 30 5 61 28 36 34 31 63 64 33 62 29 37 35 60 4 |
English ▼
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
