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IDT74ALVCH16901 Datasheet(PDF) 3 Page - Integrated Device Technology

Part No. IDT74ALVCH16901
Description  3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS / CHECKERS AND BUS-HOLD
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT74ALVCH16901 Datasheet(HTML) 3 Page - Integrated Device Technology

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INDUSTRIALTEMPERATURERANGE
IDT74ALVCH16901
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
3
FUNCTION TABLE(1,2)
Inputs
Outputs
CLKENAB
OEAB
LEAB
CLKAB
xAx
xBx
XH
X
X
X
Z
XL
H
X
L
L
XL
H
X
H
H
HL
L
X
X
B(3)
LL
L
↑
LL
LL
L
↑
HH
LL
L
L
X
B(3)
LL
L
H
X
B(4)
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW-to-HIGH Transition
2. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA,
and CLKENBA.
3. Output level before the indicated steady-state conditions were established.
4. Output level before the indicated steady-state conditions were established,
provided that CLKAB was LOW before LEAB went LOW.
PARITY ENABLE
Inputs
SEL OEBA OEAB
Operation or Function
L
H
L
Parity is checked on port A and is generated on port B.
L
L
H
Parity is checked on port B and is generated on port A.
L
H
H
Parity is checked on port B and port A.
L
L
L
Parity is generated on port A and B if device is in FF
mode.
H
L
L
Parity functions are
QA data to B, QB data to A
H
L
H
disabled; device acts as
QB data to A
H
H
L
a standard 18-bit
QA data to B
H
H
H
registered transceiver.
Isolation
PARITY
Inputs
Outputs
∑
∑
∑
∑
∑ OF INPUTS
∑
∑
∑
∑
∑ OF INPUTS
SEL
OEBA OEAB
ODD/EVEN
A1-
−−−−−A8 = H
B1—
−−−−−B8 = H
xAPAR
xBPAR
xAPAR
xERRA
xBPAR
xERRB
L
H
L
L
0, 2, 4, 6, 8
N/A
L
N/A
N/A
H
L
Z
L
H
L
L
1, 3, 5, 7
N/A
L
N/A
N/A
L
H
Z
L
H
L
L
0, 2, 4, 6, 8
N/A
H
N/A
N/A
L
L
Z
L
H
L
L
1, 3, 5, 7
N/A
H
N/A
N/A
H
H
Z
L
L
H
L
N/A
0, 2, 4, 6, 8
N/A
L
L
Z
N/A
H
L
L
H
L
N/A
1, 3, 5, 7
N/A
L
H
Z
N/A
L
L
L
H
L
N/A
0, 2, 4, 6, 8
N/A
H
L
Z
N/A
L
L
L
H
L
N/A
1, 3, 5, 7
N/A
H
H
Z
N/A
H
L
H
L
H
0, 2, 4, 6, 8
N/A
L
N/A
N/A
L
H
Z
L
H
L
H
1, 3, 5, 7
N/A
L
N/A
N/A
H
L
Z
L
H
L
H
0, 2, 4, 6, 8
N/A
H
N/A
N/A
H
H
Z
L
H
L
H
1, 3, 5, 7
N/A
H
N/A
N/A
L
L
Z
L
L
H
H
N/A
0, 2, 4, 6, 8
N/A
L
H
Z
N/A
L
L
L
H
H
N/A
1, 3, 5, 7
N/A
L
L
Z
N/A
H
L
L
H
H
N/A
0, 2, 4, 6, 8
N/A
H
H
Z
N/A
H
L
L
H
H
N/A
1, 3, 5, 7
N/A
H
L
Z
N/A
L
L
H
H
L
0, 2, 4, 6, 8
0, 2, 4, 6, 8
L
L
N/A
H
N/A
H
L
H
H
L
1, 3, 5, 7
1, 3, 5, 7
L
L
N/A
L
N/A
L
L
H
H
L
0, 2, 4, 6, 8
0, 2, 4, 6, 8
H
H
N/A
L
N/A
L
L
H
H
L
1, 3, 5, 7
1, 3, 5, 7
H
H
N/A
H
N/A
H
L
H
H
H
0, 2, 4, 6, 8
0, 2, 4, 6, 8
L
L
N/A
L
N/A
L
L
H
H
H
1, 3, 5, 7
1, 3, 5, 7
L
L
N/A
H
N/A
H
L
H
H
H
0, 2, 4, 6, 8
0, 2, 4, 6, 8
H
H
N/A
H
N/A
H
L
H
H
H
1, 3, 5, 7
1, 3, 5, 7
H
H
N/A
L
N/A
L
L
L
L
L
N/A
N/A
N/A
N/A
PE(1)
ZPE(1)
Z
L
L
L
H
N/A
N/A
N/A
N/A
PO(2)
ZPO(2)
Z
NOTES:
1. Parity output is set to the level so that the specific bus side is set to even parity.
2. Parity output is set to the level so that the specific bus side is set to odd parity.


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