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IDT74ALVCH16901 Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT74ALVCH16901 Datasheet(HTML) 2 Page - Integrated Device Technology |
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INDUSTRIALTEMPERATURERANGE 2 IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY TSSOP TOP VIEW PIN CONFIGURATION Symbol Description Max Unit VTERM(2) Terminal Voltage with Respect to GND –0.5 to +4.6 V VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V TSTG Storage Temperature –65 to +150 °C IOUT DC Output Current –50 to +50 mA IIK Continuous Clamp Current, ±50 mA VI < 0 or VI > VCC IOK Continuous Clamp Current, VO < 0 –50 mA ICC Continuous Current through each ±100 mA ISS VCC or GND ABSOLUTE MAXIMUM RATINGS(1) NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. NOTE: 1. As applicable to the device type. Symbol Parameter(1) Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 5 7 pF COUT Output Capacitance VOUT = 0V 7 9 pF COUT I/O Port Capacitance VIN = 0V 7 9 pF CAPACITANCE (TA= +25°C, F = 1.0MHz) 1 CLKENAB LEAB CLKAB 1 ERRA VCC GND 1 A1 VCC 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 56 57 58 59 60 61 62 63 64 1 VCC GND VCC GND GND 25 26 27 28 40 39 38 37 2 BPAR CLKBA 2 CLKENAB SEL 29 30 31 32 36 35 34 33 2 CLKENBA 1 APAR GND 1 CLKENBA LEBA 1 ERRB 1 BPAR GND 1 A2 1 A3 1 A4 1 A5 1 A6 1 B1 1 B2 1 B3 1 B4 1 B5 1 B6 1 A7 1 A8 2 A1 1 B7 1 B8 2 B1 2 A2 2 B2 2 A3 2 B3 GND GND 2 B4 2 B5 2 A4 2 A5 2 A6 2 A8 2 A7 2 B6 2 B7 2 B8 OEAB 2 ERRA 2 APAR ODD/EVEN 2 ERRB OEBA NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os. Pin Names Description OEAB A-to-B Output Enable Input (Active LOW) OEBA B-to-A Output Enable Input (Active LOW) LEAB A-to-B Latch Enable Input LEBA B-to-A Latch Enable Input xCLKENAB A-to-B 9-bit Clock Enables xCLKENBA B-to-A 9-bit Clock Enables CLKAB A-to-B Clock Input CLKBA B-to-A Clock Input xERRA A Error-Signal Outputs xERRB B Error-Signal Outputs xAPAR A Port Parities xBPAR B Port Parities ODD/EVEN Parity Select Input SEL Parity Enables xAx A-to-B Data Inputs or B-to-A 3-State Outputs (1) xBx B-to-A Data Inputs or A-to-B 3-State Outputs (1) PIN DESCRIPTION |
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