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DS1543 Datasheet(PDF) 3 Page - Dallas Semiconductor |
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DS1543 Datasheet(HTML) 3 Page - Dallas Semiconductor |
3 / 17 page DS1543 3 of 17 DS1543 BLOCK DIAGRAM Figure 1 DS1543 OPERATING MODES Table 1 VCC CE OE WE DQ0-DQ7 A0-A12 MODE POWER VIH X X HIGH-Z X DESELECT STANDBY VIL XVIL DIN AIN WRITE ACTIVE VIL VIL VIH DOUT AIN READ ACTIVE In Tolerance VIL VIH VIH HIGH-Z AIN READ ACTIVE VBAT < VCC < Tolerance X X X HIGH-Z X DESELECT CMOS STANDBY <VBAT X X X HIGH-Z X DATA RETENTION BATTERY CURRENT DATA READ MODE The DS1543 is in the read mode whenever CE (chip enable) is low and WE (write enable) is high. The device architecture allows ripple through access to any valid address location. Valid data will be available at the DQ pins within tAA after the last address input is stable, providing that CE and OE access times are satisfied. If CE or OE access times are not met, valid data will be available at the latter of chip enable access (tCEA) or at output enable access time (tOEA). The state of the data input/output pins (DQ) is controlled by CE and OE . If the outputs are activated before tAA, the data lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate until the next address access. DATA WRITE MODE The DS1543 is in the write mode whenever WE and CE are in their active state. The start of a write is referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout the cycle. CE and WE must return inactive for a minimum of tWR prior to the initiation of a subsequent read or write cycle. Data in must be valid tDS prior to the end of the write and remain valid for tDH afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be |
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