15 / 15 page
CY28RS480
Document #: 38-07638 Rev. *C
Page 15 of 15
Document History Page
Document Title: CY28RS480 Clock Generator for ATI RS480 Chipset
Document Number: 38-07638
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
204582
See ECN
RGL
New data sheet
*A
215828
See ECN
RGL
Minor change: posted to external web site
*B
267850
See ECN
RGL
Changed pins 10 and 11 from internal Pull up to Pull down
Changed polarity of CLKREQ#
Added register byte 3 bits [1:3] for CPU Stop control
Changed the Slew rate to max of 6.5V/ns
Changed the IDD max load from 400 to 450 mA
Changed the IPD Outputs Driven from 70 to 75 mA
Changed the CPU Duty Cycle from 45 to 53 to 45 to 55%
Changed the HTT66 Cycle to cycle jitter from 300 to 450 ps
Fixed the Single-ended loading diagram
*C
325360
See ECN
RGL
Fixed the ordering information table to match the parts in the DevMaster
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
