AS4C1M16F5
4/11/01; v.0.9.1
Alliance Semiconductor
P. 7 of 21
®
Notes
1ICC1, ICC3, and ICC4 are dependent on frequency.
2ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open.
3
An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after
extended periods of bias without clocks (greater than 8 ms).
4
AC Characteristics assume tT = 2 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, VIL (min) ≥ GND and VIH
(max)
≤ V
CC.
5VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
6
Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the
specified tRCD (max) limit, then access time is controlled exclusively by tCAC.
7
Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the
specified tRAD (max) limit, then access time is controlled exclusively by tAA.
8
Assumes three state test load (5 pF and a 380
Ω Thevenin equivalent).
9Either tRCH or tRRH must be satisfied for a read cycle.
10 tOFF (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. tOFF is referenced from
rising edge of RAS or CAS, whichever occurs last.
11 tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only.
If tWS ≥ tWS (min) and tWH ≥ tWH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the
cycle. If tRWD ≥ tRWD (min), tCWD ≥ tCWD (min) and tAWD ≥ tAWD (min), the cycle is a read-write cycle and the data out will contain data read from the
selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
12 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.
13 Access time is determined by the longest of tCAA or tCAC or tCPA
14 tASC ≥ tCP to achieve tPC (min) and tCPA (max) values.
15 These parameters are sampled and not 100% tested.
16 These characteristics apply to AS4C1M16F5 5V devices.
AC test conditions
Key to switching waveforms
- Access times are measured with output reference levels
of VOH = 2.4V and VOL = 0.4V,
VIH = 2.4V and VIL = 0.8V
- Input rise and fall times: 2 ns
100 pF*
R2 = 295
Ω
R1 = 828
Ω
Dout
GND
+5V
Figure A: Equivalent output load
*including scope
and jig capacitance
Undefined output/don’t care
Falling input
Rising input
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