64 x 4 Cascadable FIFO
64 x 5 Cascadable FIFO
CY7C401/CY7C403
CY7C402/CY7C404
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
March 1986 – Revised April 1995
1CY 7C40 2
Features
• 64 x 4 (CY7C401 and CY7C403)
64 x 5 (CY7C402 and CY7C404)
High-speed first-in first-out memory (FIFO)
• Processed with high-speed CMOS for optimum
speed/power
• 25-MHz data rates
• 50-ns bubble-through time—25 MHz
• Expandable in word width and/or length
• 5-volt power supply
± 10% tolerance, both commercial
and military
• Independent asynchronous inputs and outputs
• TTL-compatible interface
• Output enable function available on CY7C403 and
CY7C404
• Capable of withstanding greater than 2001V electro-
static discharge
• Pin compatible with MMI 67401A/67402A
Functional Description
The CY7C401 and CY7C403 are asynchronous first-in
first-out (FIFOs) organized as 64 four-bit words. The CY7C402
and CY7C404 are similar FIFOs organized as 64 five-bit
words. Both the CY7C403 and CY7C404 have an output en-
able (OE) function.
The devices accept 4- or 5-bit words at the data input (DI0 –
DIn) under the control of the shift in (SI) input. The stored
words stack up at the output (DO0 – DOn) in the order they
were entered. A read command on the shift out (SO) input
causes the next to last word to move to the output and all data
shifts down once in the stack. The input ready (IR) signal acts
as a flag to indicate when the input is ready to accept new data
(HIGH), to indicate when the FIFO is full (LOW), and to provide
a signal for a cascading. The output ready (OR) signal is a flag
to indicate the output contains valid data (HIGH), to indicate
the FIFO is empty (LOW), and to provide a signal for cascad-
ing.
Parallel expansion for wider words is accomplished by logical-
ly ANDing the IR and OR signals to form composite signals.
Serial expansion is accomplished by tying the data inputs of
one device to the data outputs of the previous device. The IR
pin of the receiving device is connected to the SO pin of the
sending device, and the OR pin of the sending device is con-
nected to the SI pin of the receiving device.
Reading and writing operations are completely asynchronous,
allowing the FIFO to be used as a buffer between two digital
machines of widely differing operating frequencies. The
25-MHz operation makes these FIFOs ideal for high-speed
communication and controller applications.
CY7C402
CY7C404
Logic Block Diagram
Pin Configurations
C401–1
C401–2
C401–3
1
2
3
4
5
6
7
8
12
11
10
9
13
16
15
14
(CY7C401) NC
(CY7C403) OE
IR
SI
DI 0
DI 1
VCC
SO
OR
DO 0
DO 1
DO 3
MR
DO 2
DI 2
DI 3
GND
20
4
5
6
7
8
32 1
19
910111213
18
17
16
15
14
SI
DI 0
DI 1
DI 2
DO 0
DO 1
NC
DO 2
OR
NC
INPUT
CONTROL
LOGIC
SI
IR
DATAIN
DI 0
DI 1
DI 2
DI 3
(DI 4)
MASTER
RESET
MR
WRITE MULTIPLEXER
WRITE POINTER
READ MULTIPLEXER
READ POINTER
MEMORY
ARRAY
OUTPUT
CONTROL
LOGIC
DATAIN
OUTPUT
ENABLE
OE
DO0
DO1
DO2
DO3
(DO 4)
SO
OR
1
2
3
4
5
6
7
8
14
13
12
11
15
18
17
16
IR
SI
DI 0
DI 1
VCC
SO
OR
DO0
DO1
DO3
DO4
DO2
DI 2
DI 3
DI 4
CY7C401
CY7C403
(CY7C402) NC
(CY7C404) OE
9
10
MR
GND
CY7C401
CY7C403
C401–4
20
4
5
6
7
8
32 1
19
910111213
18
17
16
15
14
C401–5
SI
DI 0
DI 1
DI 2
DO 0
DO 1
DO 2
OR
DO 3
DI 3
CY7C402
CY7C404
LCC
DIP
LCC
DIP
Selection Guide
7C401/2–5
7C40X–10
7C40X–15
7C40X–25
Operating Frequency (MHz)
5
10
15
25
Maximum Operating
Current (mA)
Commercial
75
75
75
75
Military
90
90
90
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