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HY57V561620 Datasheet(PDF) 2 Page - Hynix Semiconductor

Part No. HY57V561620
Description  4Banks x 4M x 16Bit Synchronous DRAM
Download  13 Pages
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

HY57V561620 Datasheet(HTML) 2 Page - Hynix Semiconductor

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HY57V561620(L)T
Revision 1.8 / Apr.01
PIN CONFIGURATION
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
54pin TSOP II
400mil x 875mil
0.8mm pin pitch
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
CLK
Clock
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
CS
Chip Select
Enables or disables all inputs except CLK, CKE, UDQM and LDQM
BA0, BA1
Bank Address
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A12
Address
Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
RAS, CAS, WE
Row Address Strobe, Col-
umn Address Strobe, Write
Enable
RAS, CAS and WE define the operation
Refer function truth table for details
UDQM, LDQM
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ15
Data Input/Output
Multiplexed data input / output pin
VDD/VSS
Power Supply/Ground
Power supply for internal circuits and input buffers
VDDQ/VSSQ
Data Output Power/Ground
Power supply for output buffers
NC
No Connection
No connection


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