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PEB2055 Datasheet(PDF) 11 Page - Siemens Semiconductor Group |
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PEB2055 Datasheet(HTML) 11 Page - Siemens Semiconductor Group |
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11 / 269 page  PEB 2055 PEF 2055 Overview Semiconductor Group 11 1.3 Pin Definitions and Functions Pin No. EPIC-S EPIC Symbol Input (I) Output (O) Function 30 30 CS I Chip Select; active low. A “low” on this line selects the EPIC for read/write operations. 29 29 WR, R/W I Write, active low, Siemens/Intel bus mode. When “low”, a write operation is indicated. Read/Write, Motorola bus mode. When “high” a valid µP-access identifies a read operation, when “low” it identifies a write access. 28 28 RD, DS I Read, active low, Siemens/Intel bus mode. When “low” a read operation is indicated. Data Strobe, Motorola bus mode. A rising edge marks the end of a read or write operation. 19 20 21 22 23 24 25 26 19 20 21 22 23 24 25 26 AD0, D0 AD1, D1 AD2, D2 AD3, D3 AD4, D4 AD5, D5 AD6, D6 AD7, D7 I/O I/O I/O I/O I/O I/O I/O I/O Address/Data Bus; multiplexed bus mode. Transfers addresses from the µP-system to the EPIC and data between the µP and the EPIC. Data Bus; demultiplexed bus mode. Transfers data between the µP and the EPIC. When driving data the pins have push pull characteristic, otherwise they are in high impedance state. 31 31 ALE I Address Latch Enable ALE controls the on chip address latch in multiplexed bus mode. While ALE is “high”, the latch is transparent. The falling edge latches the current address. During the first read/write access following reset ALE is evaluated to select the bus mode. 32 32 INT O (OD) Interrupt Request, active low. This signal is activated when the EPIC requests an interrupt. Due to the open drain (OD) characteristic of INT multiple interrupt sources can be connected together. 44 44 RES I Reset A “high” forces the EPIC into reset state. 16 16 PFS I PCM Interface Frames Synchronization |
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