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KMM372V3200CS1 Datasheet(PDF) 5 Page - Samsung semiconductor

Part No. KMM372V3200CS1
Description  32M x 72 DRAM DIMM with ECC using 16Mx4, 4K 8K Refresh, 3.3V
Download  18 Pages
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Maker  SAMSUNG [Samsung semiconductor]
Homepage  http://www.samsung.com/Products/Semiconductor
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KMM372V3200CS1 Datasheet(HTML) 5 Page - Samsung semiconductor

 
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DRAM MODULE
KMM372V320(8)0CS1
AC CHARACTERISTICS (0
°C≤TA≤70°C, VCC=3.3V±0.3V. See notes 1,2.)
Parameter
Symbol
-5
-6
Unit
Note
Min
Max
Min
Max
CAS setup time(CAS-before-RAS refresh)
tCSR
10
10
ns
11
CAS hold time(CAS-before-RAS refresh)
tCHR
8
8
ns
11
RAS to CAS precharge time
tRPC
3
3
ns
11
Access time from CAS precharge
tCPA
35
40
ns
3,11
Fast page mode cycle time
tPC
35
40
ns
Fast page mode read-modify-write cycle time
tPRWC
76
85
ns
CAS precharge time(Fast page cycle)
tCP
10
10
ns
RAS pulse width(Fast page cycle)
tRASP
50
200K
60
200K
ns
RAS hold time from CAS precharge
tRHCP
35
40
ns
11
W to RAS precharge time(C-B-R refresh)
tWRP
15
15
ns
11
W to RAS hold time(C-B-R refresh)
tWRH
8
8
ns
11
OE access time
tOEA
18
20
ns
11
OE to data delay
tOED
18
20
ns
11
Output buffer turn off delay time from OE
tOEZ
5
18
5
20
ns
11
OE command hold time
tOEH
13
15
ns
PDE to Valid PD bit
tPD
10
10
ns
PDE to PD bit Inactive
tPDOFF
2
7
2
7
ns
Present Detect Read Cycle
NOTES
An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are ref-
erence levels for measuring timing of input signals. Transi-
tion times are measured between VIH(min) and VIL(max) and
are assumed to be 5ns for all inputs.
Measured with a load equivalent to 1 TTL loads and 100pF.
Operation within the
tRCD(max) limit insures that tRAC(max)
can be met.
tRCD(max) is specified as a reference point only.
If
tRCD is greater than the specified tRCD(max) limit, then
access time is controlled exclusively by
tCAC.
Assumes tha
tRCD
tRCD(max).
This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to VOH or
VOL.
tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operat-
ing parameter. They are included in the data sheet as electri-
cal characteristics only. If
tWCS
tWCS(min) the cycle is an
early write cycle and the data out pin will remain high imped-
ance for the duration of the cycle. If
tRWD
tRWD(min),
tCWD
tCWD(min), tAWDtAWD(min) and tCPWDtCPWD(min).
The cycle is a read-modify-write cycle and the data out will
contain data read from the selected cell. If neither of the
above sets of conditions is satisfied, the condition of data
out(at access time) is indeterminate.
Either
tRCH or tRRH must be satisfied for a read cycle.
These parameters are referenced to the CAS leading edge in
early write cycles.
Operation within the
tRAD(max) limit insures that tRAC(max)
can be met.
tRAD(max) is specified as reference point only. If
tRAD is greater than the specified tRAD(max) limit, then
access time is controlled by
tAA.
The timing skew from the DRAM to the DIMM resulted from
the addition of buffers.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.


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