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IDT71V124 Datasheet(PDF) 6 Page - Integrated Device Technology

Part No. IDT71V124
Description  3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Revolutionary Pinout
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT71V124 Datasheet(HTML) 6 Page - Integrated Device Technology

   
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6.42
6
IDT71V124, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit), Revolutionary Pinout
Commercial and Industrial Temperature Ranges
PAR
T IN
OBSOLESCENCE
ORDER
71V124SA
FOR
NEW
DESIGNS
Timing Waveform of Write Cycle No.1 (WE Controlled Timing)(1,2,4)
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4)
NOTES:
1. A write occurs during the overlap of a LOW
CS and a LOW WE.
2.
OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If
OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the
CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS must be active during the tCW write
period.
5. Transition is measured ±200mV from steady state.
ADDRESS
CS
WE
DATAOUT
DATAIN
3484 drw 07
(5)
(2)
(5)
(5)
DATAIN VALID
HIGH IMPEDANCE
tWC
tAW
tAS
tWHZ
tWP
tCHZ
tOW
tDW
tDH
tWR
(3)
(3)
CS
ADDRESS
DATAIN
3484 drw 08
tAW
tWC
tCW
tAS
tWR
tDW
tDH
DATAIN VALID
WE
(3)


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