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74LCX125MTR Datasheet(PDF) 1 Page - STMicroelectronics |
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74LCX125MTR Datasheet(HTML) 1 Page - STMicroelectronics |
1 / 12 page 1/12 September 2004 s 5V TOLERANT INPUTS AND OUTPUTS s HIGH SPEED: tPD = 5.2 ns (MAX.) at VCC = 3V s POWER DOWN PROTECTION ON INPUTS AND OUTPUTS s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V s PCI BUS LEVELS GUARANTEED AT 24 mA s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC(OPR) = 2.0V to 3.6V (1.5V Data Retention) s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 125 s LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17) s ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V DESCRIPTION The 74LCX125 is a low voltage CMOS QUAD BUS BUFFER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to 5V signal environment for both inputs and outputs. The device requires the 3-STATE control input G to be set high to place the output in to the high impedance state. It has same speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74LCX125 LOW VOLTAGE CMOS QUAD BUS BUFFER (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS Figure 1: Pin Connection And IEC Logic Symbols Table 1: Order Codes PACKAGE T & R SOP 74LCX125MTR TSSOP 74LCX125TTR TSSOP SOP Rev. 5 |
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