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RD28F3204C3B70 Datasheet(PDF) 11 Page - Intel Corporation |
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RD28F3204C3B70 Datasheet(HTML) 11 Page - Intel Corporation |
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11 / 70 page  3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family Datasheet 11 2.0 Principles of Operation The flash memory utilizes a CUI and automated algorithms to simplify program and erase operations. The WSM automates program and erase operations by handling data and address latches, WE#, and system status requests. . 2.1 Bus Operation All bus cycles to or from the Stacked-CSP conform to standard microcontroller bus cycles. Four control signals dictate the data flow in and out of the flash component: F-CE#, F-OE#, F-WE# and F-RP#. Four separate control signals handle the data flow in and out of the SRAM component: S-CS1#, S-CS2, S-OE#, and S-WE#. These bus operations are summarized in Table 2 and Table 3. 2.1.1 Read The flash memory has four read modes: read array, read identifier, read status and CFI query. These flash memory read modes are not dependent on the F-VPP voltage. Upon initial device power-up or after exit from reset, the flash device automatically defaults to read array mode. F-CE# and F-OE# must be asserted to obtain data from the flash component. The SRAM has one read mode available. S-CS1#, S-CS2, and S-OE# must be asserted to obtain data from the SRAM device. See Table 3, “3 Volt Intel Advanced+ Boot Block Flash Memory Stacked-CSP Bus Operations” on page 12 for a summary of operations. Figure 2. 3 Volt Intel® Advanced+ Boot Block Stacked Chip Scale Package Block Diagram F-VCC F-OE# F-CE# A[Max:0] 2-, 4- or 8-Mbit SRAM 28F160C3 or 28F320C3 Flash S-VCC F-VCCQ S-CS1 S-CS2 S-OE# S-WE# S-UB# S-LB# F-VPP F-WE# F-VSS S-VSS D[15:0] F-WP# F-RP# |
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