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SN74HC573A-Q1 Datasheet(PDF) 1 Page - Texas Instruments

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Part No. SN74HC573A-Q1
Description  OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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SN74HC573A-Q1 Datasheet(HTML) 1 Page - Texas Instruments

   
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SN74HC573AQ1
OCTAL TRANSPARENT DTYPE LATCH
WITH 3STATE OUTPUTS
SCLS600 − NOVEMBER 2004
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Qualification in Accordance With
AEC-Q100
D Qualified for Automotive Applications
D Customer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
D Wide Operating Voltage Range of 2 V to 6 V
D High-Current 3-State Outputs Drive Bus
Lines Directly or up to 15 LSTTL Loads
D Low Power Consumption, 80-µA Max ICC
D Typical tpd = 21 ns
D ±6-mA Output Drive at 5 V
D Low Input Current of 1 µA Max
D Bus-Structured Pinout
† Contact factory for details. Q100 qualification data available on
request.
description/ordering information
This octal transparent D-type latch features 3-state outputs designed specifically for driving highly capacitive
or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the
outputs are latched to retain the data that was set up.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40
°C to 125°C
SOIC − DW
Reel of 2500
SN74HC573AQDWRQ1
HC573AQ
−40
°C to 125°C
TSSOP − PW
Reel of 2000
SN74HC573AQPWRQ1
HC573AQ
‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DW OR PW PACKAGE
(TOP VIEW)
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OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
Copyright
 2004, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.


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