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THNCF256MBAI Datasheet(PDF) 11 Page - Toshiba Semiconductor |
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THNCF256MBAI Datasheet(HTML) 11 Page - Toshiba Semiconductor |
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11 / 48 page  THNCFxxxMBA/BAI Series 2002-10-20 11/48 Preliminary 2. Task File register access specifications There are two cases of Task File register mapping, one is mapped I/O address area, the other is mapped Memory address area. Each case of Task File registers read and write operations is executed under the condition as follows. That area can be accessed by Byte/World/Odd Byte modes, which are defined by PC card standard specifications. (1) I/O address map • Task File Register Read Access Mode (1) Mode −REG −CE2 −CE1 A0 −IORD −IOWR −OE −WE D8 to D15 D0 to D7 Standby mode X H H X X X X X High-Z High-Z L H L L L H H H High-Z even byte Byte access (8bit) L H L H L H H H High-Z odd byte Word access (16bit) L L L X L H H H odd byte even byte Odd byte access (8bit) L L H X L H H H odd byte High-Z Note: X → L or H • Task File Register Write Access Mode (1) Mode −REG −CE2 −CE1 A0 −IORD −IOWR −OE −WE D8 to D15 D0 to D7 Standby mode X H H X X X X X Don’t care Don’t care L H L L H L H H Don’t care even byte Byte access (8bit) L H L H H L H H Don’t care odd byte Word access (16bit) L L L X H L H H odd byte even byte Odd byte access (8bit) L L H X H L H H odd byte Don’t care Note: X → L or H • Task File Register Access Timing Example (1) −CE2/−CE1 −IOWR −IORD D0~D15 −REG A0~A10 Dout Din Read cycle Write cycle |
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