7 / 15 page
CY7C138
CY7C139
7
Notes:
19. BUSY = HIGH for the writing port.
20. CEL = CER = LOW.
21. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the
bus for the required tSD. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as short as the specified
tPWE.
23. R/W must be HIGH during all address transitions.
Switching Waveforms (continued)
VALID
tDDD
tWDD
MATCH
MATCH
R/WR
DATA INR
DATAOUTL
C138-10
tWC
ADDRESS R
t
PWE
VALID
t
SD
t
HD
ADDRESS L
Read Timing with Port-to-Port Delay (M/S = L)
[19, 20]
C138-11
tAW
tWC
DATA VALID
HIGH IMPEDANCE
tSCE
tSA
tPWE
tHD
tSD
tHA
tHZOE
t
LZOE
SEM OR CE
R/W
OE
DATA OUT
DATA IN
ADDRESS
Write Cycle No. 1: OE Three-States Data I/Os (Either Port)
[21, 22, 23]
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
