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CY28322-2 Datasheet(PDF) 3 Page - Cypress Semiconductor

Part No. CY28322-2
Description  133-MHz Spread Spectrum Clock Synthesizer with Differential CPU Outputs
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY28322-2 Datasheet(HTML) 3 Page - Cypress Semiconductor

 
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PRELIMINARY
CY28322-2
Document #: 38-07145 Rev. *B
Page 3 of 17
Serial Data Interface (SMBus)
To enhance the flexibility and function of the clock synthesizer,
a two signal SMBus interface is provided according to SMBus
specification. Through the Serial Data Interface, various
device functions such as individual clock output buffers, can
be individually enabled or disabled. CY28322-2 supports both
block read and block write operations.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts only block writes from
the controller. The bytes must be accessed in sequential order
from lowest to highest byte, (most significant bit first) with the
ability to stop after any complete byte has been transferred.
Indexed bytes are not allowed.
A block write begins with a slave address and a WRITE
condition. The R/W bit is used by the SMBus controller as a
data direction bit. A zero indicates a WRITE condition to the
clock device. The slave receiver address is 11010010 (D2h).
A command code of 0000 0000 (00h) and the byte count bytes
are required for any transfer. After the command code, the
core logic issues a byte count which describes number of
additional bytes required for the transfer, not including the
command code and byte count bytes. For example, if the host
has 20 data bytes to send, the first byte would be the number
20 (14h), followed by the 20 bytes of data. The byte count byte
is required to be a minimum of 1 byte and a maximum of 32
bytes It may not be 0. Figure 1 shows an example of a block
write.
A transfer is considered valid after the acknowledge bit corre-
sponding to the byte count is read by the controller.
Clock Driver Impedances
Buffer
VDD Range
Buffer Type
Impedance
Min.
Typ.
Max.
CPU, CPU#
Type X1
50
REF
3.135–3.465
Type 3
20
40
60
PCI, 3V66, 66BUFF
3.135–3.465
Type 5
12
30
55
USB
3.135–3.465
Type 3A
12
30
55
DOT
3.135–3.465
Type 3B
12
30
55
Clock Enable Configuration
PWR_DWN# CPU_STOP#
PCI_STOP#
CPU
CPU#
3V66
66BUFF
PCI_F
PCI
USB/DOT
VCOS/
OSC
0
X
X
IREF*2
FLOAT
LOW
LOW
LOW
LOW
LOW
OFF
1
0
0
IREF*2
FLOAT
ON
ON
ON
OFF
ON
ON
1
0
1
IREF*2
FLOAT
ON
ON
ON
ON
ON
ON
1
1
0
ON
ON
ON
ON
ON
OFF
ON
ON
11
1
ON
ON
ON
ON
ON
ON
ON
ON
Start
Bit
Slave Address
1 1 0 1 0 0 1 0
R/W
0/1
A
Command
Code
0 0 0 0 0 0 0 0
AByte Count =
N
A
Data Byte 0
A
. . .
Data Byte N-1 AStop
Bit
1 bit
7 bits
1
1
8 bits
1
8 bits
1
8 bits
1
8 bits
1
1 bit
Figure 1. An Example of a Block Write
From Master to Slave
From Slave to Master


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