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CY28322-2 Datasheet(PDF) 2 Page - Cypress Semiconductor

Part No. CY28322-2
Description  133-MHz Spread Spectrum Clock Synthesizer with Differential CPU Outputs
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY28322-2 Datasheet(HTML) 2 Page - Cypress Semiconductor

 
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PRELIMINARY
CY28322-2
Document #: 38-07145 Rev. *B
Page 2 of 17
Pin Summary
Pin Name
Pin Number
Pin Description
REF0
47
3.3V 14.318-MHz clock output
XTAL_IN
1
14.318-MHz crystal input
XTAL_OUT
2
14.318-MHz crystal input
CPU, CPU# [1:2]
43, 39, 42, 38
Differential CPU clock outputs
3V66_0
29
3.3V 66-MHz clock output
3V66_1/VCH
31
3.3V selectable through SMBus to be 66 MHz or 48 MHz
66IN/3V66_5
20
66-MHz input to buffered 66BUFF and PCI or 66-MHz clock from internal VCO
66BUFF [2:0] /3V66 [4:2] 17, 18, 19
66-MHz buffered outputs from 66Input or 66-MHz clocks from internal VCO
PCI_F [0:2]
4, 5, 6
33 MHz clocks divided down from 66Input or divided down from 3V66
PCI [0:5]
8, 9, 10, 12, 13, 14 PCI clock outputs divided down from 66Input or divided down from 3V66
USB
35
Fixed 48-MHz clock output
DOT
34
Fixed 48-MHz clock output
S2
36
Special 3.3V 3-level input for Mode selection
S1
46
3.3V LVTTL inputs for CPU frequency selection
IREF
37
A precision resistor is attached to this pin which is connected to the internal
current reference
PWR_DWN#
21
3.3V LVTTL input for Power_Down# (active LOW)
PCI_STOP#
30
3.3V LVTTL input for PCI_STOP# (active LOW)
CPU_STOP#
45
3.3V LVTTL input for CPU_STOP# (active LOW)
PWRGD#
24
3.3V LVTTL input is a level sensitive strobe used to determine when S[2:1] inputs
are valid and OK to be sampled (Active LOW). Once PWRGD# is sampled LOW,
the status of this output will be ignored.
SDATA
25
SMBus compatible SDATA
SCLK
26
SMBus compatible Sclk
VDD_PCI, VDD_3V66,
VDD_CPU,VDD_REF
11, 15, 28, 40, 44,
48
3.3V power supply for outputs
VDD_48 MHz
33
3.3V power supply for 48 MHz
VDD_CORE
22
3.3V power supply for PLL
GND_REF, GND_PCI,
GND_3V66, GND_IREF,
GND_CPU
3, 7, 16, 27, 32, 41 Ground for outputs
GND_CORE
23
Ground for PLL
Function Table[1]
S2
S1 CPU (MHz)
3V66[0:1]
(MHz)
66BUFF[0:2]/3
V66[2:4] (MHz)
66IN/3V66_5
(MHz)
PCI_F/PCI
(MHz)
REF0(MHz)
USB/DOT
(MHz)
Notes
1
0
100 MHz
66 MHz
66IN
66 MHz Input
66IN/2
14.318 MHz
48 MHz
2, 3, 4
1
1
133 MHz
66 MHz
66IN
66 MHz Input
66IN/2
14.318 MHz
48 MHz
2, 3, 4
0
0
100 MHz
66 MHz
66 MHz
66 MHz
33 MHz
14.318 MHz
48 MHz
2, 3, 4
0
1
133 MHz
66 MHz
66 MHz
66 MHz
33 MHz
14.318 MHz
48 MHz
2, 3, 4
Mid
0
TCLK/2
TCLK/4
TCLK/4
TCLK/4
TCLK/8
TCLK
TCLK/2
7, 8, 5
Mid
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Notes:
1.
TCLK is a test clock driven in on the XTALIN input in test mode.
2.
“Normal” mode of operation
3.
Range of reference frequency allowed is min. = 14.316 nominal = 14.31818 MHz, max = 14.32 MHz.
4.
Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
5.
Mid is defined a voltage level between 1.0V and 1.8V for 3 level input functionality. Low is below 0.8V. High is above 2.0V.
6.
Required for DC output impedance verification.
7.
These modes are to use the same internal dividers as the CPU = 200-MHz mode. The only change is to slow down the internal VCO to allow under clock
margining.
8.
All parameters specified with loaded outputs.


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