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CY28322-2 Datasheet(PDF) 5 Page - Cypress Semiconductor

Part No. CY28322-2
Description  133-MHz Spread Spectrum Clock Synthesizer with Differential CPU Outputs
Download  17 Pages
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY28322-2 Datasheet(HTML) 5 Page - Cypress Semiconductor

 
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PRELIMINARY
CY28322-2
Document #: 38-07145 Rev. *B
Page 5 of 17
Data Byte 3
Bit
Pin#
Name
Pin Description
Type
Power-on
Default
Bit 7
34
DOT
DOT 48-MHz Output Enable
R/W
1
Bit 6
35
USB
USB 48-MHz Output Enable
R/W
1
Bit 5
6
PCI_F2
Allow control of PCI_F2 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
R/W
0
Bit 4
5
PCI_F1
Allow control of PCI_F1 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
R/W
0
Bit 3
4
PCI_F0
Allow control of PCI_F0 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
R/W
0
Bit 2
6
PCI_F2
PCI_F2 Output Enable
R/W
1
Bit 1
5
PCI_F1
PCI_F1Output Enable
R/W
1
Bit 0
4
PCI_F0
PCI_F0 Output Enable
R/W
1
Data Byte 4
Bit
Pin#
Name
Pin Description
Type
Power-on
Default
Bit 7
TBD
N/A
R0
Bit 6
TBD
N/A
R0
Bit 5
29
3V66_0
3V66_0 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 4
31
3V66_1/VCH
3V66_1/VCH Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 3
20
66IN/3V66_5
3V66_5 Output Enable
1 = Enable; 0 = Disable
Note. This bit should be used when pin 24 is configured as 3v66_5 output.
Do not clear this bit when pin 24 is configured as 66IN input.
R/W
1
Bit 2
19
66BUFF2
66-MHz Buffered 2 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 1
18
66BUFF1
66-MHz Buffered 1 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 0
17
66BUFF0
66-MHz Buffered 0 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Data Byte 5
Bit
Pin#
Name
Pin Description
Type
Power-on
Default
Bit 7
N/A
N/A
R
0
Bit 6
N/A
N/A
R
0
Bit 5
66BUFF [2:0]
Tpd 66IN to 66BUFF propagation delay control
R/W
0
Bit 4
66BUFF [2:0]
R/W
0
Bit 3
DOT
DOT edge rate control
R/W
0
Bit 2
DOT
R/W
0
Bit 1
USB
USB edge rate control
R/W
0
Bit 0
USB
R/W
0
Byte 6: Vendor ID
Bit
Description
Type
Power-on
Default
Bit 7
Revision Code Bit 3
R
0
Bit 6
Revision Code Bit 2
R
0
Bit 5
Revision Code Bit 1
R
0


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