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CY28322-2 Datasheet(PDF) 4 Page - Cypress Semiconductor

Part No. CY28322-2
Description  133-MHz Spread Spectrum Clock Synthesizer with Differential CPU Outputs
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY28322-2 Datasheet(HTML) 4 Page - Cypress Semiconductor

 
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PRELIMINARY
CY28322-2
Document #: 38-07145 Rev. *B
Page 4 of 17
Data Byte Configuration Map
Data Byte 0: Control Register (0 = Enable, 1 = Disable)
Bit
Affected
Pin#
Name
Description
Type
Power-on
Default
Bit 7
4, 5, 6, 10,
11, 12, 13,
16, 17, 18,
33, 35
PCI [0:6]
CPU[2:1]
3V66[1:0]
Spread Spectrum Enable
0 = Spread Off, 1 = Spread On
R/W
0
Bit 6
TBD
TBD
R
0
Bit 5
31
3V66_1/VCH
VCH Select 66 MHz/48 MHz
0 = 66 MHz, 1 = 48 MHz
R/W
0
Bit 4
39, 43, 38,
42
CPU [2:1]
CPU# [2:1]
CPU_STOP#
Reflects the current value of the external CPU_STOP# pin
RN/A
Bit 3
8, 9, 10, 11,
12, 13, 14,
PCI [5:0]
PCI_STOP#
(Does not affect PCI_F [2:0] pins)
R/W
N/A
Bit 2
––
S2–Reflects the value of the S2 pin sampled on power-up
R
N/A
Bit 1
––
S1–Reflects the value of the S1 pin sampled on power-up
R
N/A
Bit 0
––
Reserved
R
1
Data Byte 1
Bit
Pin#
Name
Description
Type
Power-on
Default
Bit 7
N/A
CPU Mult0 Value
R
N/A
Bit 6
43,39,
CPU1:2
Three-state CPU1:2 during power-down
0 = Normal; 1 = Three-stated
R/W
0
Bit 5
38, 39
CPU2
CPU2#
Allow Control of CPU2 with assertion of CPU_STOP#
0 = Not free running; 1 = Free running
R/W
0
Bit 4
42, 43
CPU1
CPU1#
Allow Control of CPU1 with assertion of CPU_STOP#
0 = Not free running;1 = Free running
R/W
0
Bit 3
Reserved
Reserved
R/W
0
Bit 2
38, 39
CPU2
CPU2#
CPU2 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 1
42, 43
CPU1
CPU1#
CPU1Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 0
Reserved
Reserved
R/W
1
Data Byte 2
Bit
Pin#
Name
Pin Description
Type
Power-on
Default
Bit 7
N/A
N/A
R
0
Bit 6
14
PCI5
PCI5 Output Enable
1 = Enabled, 0 = Disabled
R/W
1
Bit 5
13
PCI4
PCI4 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 4
12
PCI3
PCI3 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 3
10
PCI2
PCI2Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 2
9
PCI1
PCI1 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 1
8
PCI0
PCI0 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 0
Reserved
Write to”0”
R/W
1


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