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PC8240VTPU200ETC Datasheet(PDF) 9 Page - ATMEL Corporation |
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PC8240VTPU200ETC Datasheet(HTML) 9 Page - ATMEL Corporation |
9 / 42 page 9 PC8240 2149A–HIREL–05/02 Figure 2. Supply Voltage Sequencing and Separation Cautions Notes: 1. Numbers associated with waveform separations correspond to caution numbers listed in Table 3, “Recommended Operat- ing Conditions,” on page 8. 2. Refer to “Power Supply Voltage Sequencing” on page 35 for additional information. 3. Refer to Table 9 on page 18 for additional information on PLL Relock and reset signal assertion timing requirements. 4. Refer to Table 10 on page 20 for additional information on reset configuration pin setup timing requirements. 5. HRST_CPU/HRST_CTRL must transition from a logic 0 to a logic 1 in less than one SDRAM_SYNC_IN clock cycle for the devicetobein the non-resetstate. OVdd/GVdd/(LVdd@3.3V ----) Vdd/AVdd/AVdd2/LAVdd LVdd at 5V Time 3.3V 5V 2.5V 0 7 10 9 9 10 6.8 Voltage Regulator Delay(2) Reset Configuration Pins HRST_CPU & HRST_CTRL asserted 255 external memory Clock cycles(3) 9 external memory clock cycles setup time(4) HRST_CPU & HRST_CTRL Vdd Stable (1) VM = 1.4V Maximum rise time must be less than one external memory clock cycle(5) 100 ms PLL Relock Time(3) Power Supply Ramp Up(2) |
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