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PC8240 Datasheet(PDF) 30 Page - ATMEL Corporation |
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PC8240 Datasheet(HTML) 30 Page - ATMEL Corporation |
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30 / 42 page  30 PC8240 2149A–HIREL–05/02 Notes: 1. TRST is an asynchronous signal. The setup time is for test purposes only. 2. Non-test (other than TDI and TMS) signal input timing with respect to TCK. 3. Non-test (other than TDO) signal output timing with respect to TCK. 4. Timings are independent of the system clock (PCI_SYNC_IN). Figure 21. JTAG Clock Input Timing Diagram Figure 22. JTAG TRST Timing Diagram Figure 23. JTAG Boundary Scan Timing Diagram 10 TMS, TDI Data Setup Time 5 – ns 11 TMS, TDI Data Hold Time 15 – ns 12 TCK to TDO Data Valid 0 15 ns 13 TCK to TDO High Impedance 0 15 ns Table 17. JTAG AC Timing Specifications (Independent of PCI_SYNC_IN) Num Characteristics (4) Min Max Unit Notes TCK 2 2 1 VM VM VM 3 3 VM = Midpoint Voltage 4 5 TRST_ TCK 9 8 67 TCK DATA INPUTS INPUT VALID DATA OUTPUT VALID DATA DATA OUTPUTS DATA OUTPUTS |
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