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ADP1071-1ARWZ-R7 Datasheet(PDF) 19 Page - Analog Devices |
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ADP1071-1ARWZ-R7 Datasheet(HTML) 19 Page - Analog Devices |
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19 / 27 page  Data Sheet ADP1071-1/ADP1071-2 Rev. B | Page 19 of 27 The root cause of the device exiting hiccup mode is due to the effect that the OCP hiccup mode feature has on the SS2 pin. During OCP recovery, the SS2 pin tracks the FB pin and attempts a soft start from the precharge sequence. During this time that SS2 tracks FB, the SS2 pin voltage can be less than the FB pin voltage for a short interval, which causes the COMP pin (output of the gm amplifier) to momentarily fall below the maximum COMP pin clamp level. This event means that the current limit required for the next few switching periods is less than the maximum threshold and puts the device out of hiccup mode because the ADP1071-1/ADP1071-2 fail to register 1.25 ms worth of consecutive overcurrent cycles and fails to enter OCP hiccup mode. The following scenarios guarantee OCP hiccup mode based on the configuration of the VDD2 power supply: • When VDD2 is powered directly from the output voltage, if a short circuit on the output terminals of the load occurs after steady state regulation is achieved, the VDD2 pin voltage is less than the UVLO threshold, and the device enters hiccup mode for 200 ms, similar to the hiccup time described in the Remote System Reset section. • When VDD2 is powered through auxiliary winding or another configuration, when a short circuit occurs on the output terminals, the auxiliary winding is not shorted and maintains a positive voltage above the VDD2 UVLO threshold. To enter hiccup mode, the following circuit is recommended, as shown in Figure 19. The circuit operates as follows: when the output voltage goes low due to a short circuit, the D1 diode turns on, which pulls the base of the bipolar junction transistor (BJT) low, shutting off VDD2. The system then enters hiccup mode, as described in the Remote System Reset section. R3 is sized to bias the Zener diode and R4 is sized such that (VZENER − 1)/R4 > IZENER, where VZENER is the voltage of the diode and IZENER is the biasing current of the diode. This sizing ensures that the impedance of the resistor is less than the impedance of the diode, which causes the voltage of the diode to drop, and allows VDD2 to enter UVLO. If the output voltage is <5 V, the same procedure can be used to size the R4 resistor. If a discrete LDO is not used, a simple resistor and diode connector to the output voltage is sufficient. In this case, the R4 resistor is sized to limit the current through the D1 diode when the output voltage is 0 V during a short circuit event. Because the bandwidth of the system is high, the ADP1071-1/ADP1071-2 are able to maintain voltage regulation at the proper voltage level, even if the auxiliary winding voltage is higher than the output voltage. The soft start and soft start from precharge conditions is met with the addition of this circuit due to the bandwidth of the overall system. R3 500Ω R4 100Ω VDD2 VOUT AGND2 ~6.3V ZENER D1 D1 VOUT R4 100Ω ALTERNATE OPTION FROM AUXILIARY WINDING ~10V Figure 19. Recommended Circuit to Guarantee Hiccup Mode TEMPERATURE SENSING The ADP1071-1/ADP1071-2 have an internal temperature sensor that shuts down the controller when the internal temperature exceeds the OTP limit. At this time, the primary and secondary MOSFET drivers (GATE and SR) are held low. When the temperature drops below the OTP hysteresis level, the ADP1071-1/ADP1071-2 restart with a soft start sequence. FREQUENCY SETTING (RT PIN) The switching frequency can be programmed in a range of 50 kHz to 600 kHz by connecting a resistor from RT to AGND1. A small current flows out of the RT pin and the voltage across it sets up the internal oscillator frequency. The value of this pin is approximately 1.224 V in steady state. Use the following equation to determine the resistor (in Ω) for a particular switching frequency (in kHz): 12 11 (kHz) 1000 41.67 10 S f R − = × ×× where: fS is the switching frequency. R is the resistor on the RT pin. MAXIMUM DUTY CYCLE To prevent the transformer core from saturating in the event of high current or extreme load transient, a maximum duty cycle clamp is internally set to 85%. As an added protection feature to prevent open-loop conditions, the maximum duty cycle is also applicable during soft start. If the controller reaches the maximum duty cycle during soft start for three consecutive switching periods, the 40 ms hiccup timer is initiated. FREQUENCY SYNCHRONIZATION The switching frequency of the ADP1071-1/ADP1071-2 can be synchronized to an external clock at the SYNC pin. When an external clock rising edge is first detected, it takes approx- imately seven to ten periods for the internal clock to lock in the SYNC clock frequency. In between the time that the SYNC clock is detected and the time that it is locked in, the controller continues to operate with the internal oscillator frequency. The SYNC frequency must be within ±10% of the internal oscil- lator frequency set by the RT pin. Otherwise, synchronization does not take place. |
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