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SN74AUC2G125DCUR Datasheet(PDF) 1 Page - Texas Instruments |
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SN74AUC2G125DCUR Datasheet(HTML) 1 Page - Texas Instruments |
1 / 12 page www.ti.com FEATURES DCT OR DCU PACKAGE (TOP VIEW) 1 2 3 4 8 7 6 5 1OE 1A 2Y GND VCC 2OE 1Y 2A 4 3 2 1 5 6 7 8 GND 2Y 1A 1OE 2A 1Y 2OE VCC YEP OR YZP PACKAGE (BOTTOM VIEW) DESCRIPTION/ORDERING INFORMATION SN74AUC2G125 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES532A – DECEMBER 2003 – REVISED MARCH 2005 • Available in the Texas Instruments NanoStar™ and NanoFree™ Packages • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation • Ioff Supports Partial-Power-Down Mode Operation • Sub-1-V Operable • Max tpd of 1.8 ns at 1.8 V • Low Power Consumption, 10 µA at 1.8 V • ±8-mA Output Drive at 1.8 V • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) This dual bus buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC2G125 features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high. NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. For more information about AUC Little Logic devices, please refer to the TI application report, Applications of Texas Instruments AUC Sub-1-V Little Logic Devices, literature number SCEA027. ORDERING INFORMATION TA PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING(2) NanoStar™ – WCSP (DSBGA) Tape and reel SN74AUC2G125YEPR 0.23-mm Large Bump – YEP _ _ _UM_ NanoFree™ – WCSP (DSBGA) Tape and reel SN74AUC2G125YZPR –40°C to 85°C 0.23-mm Large Bump – YZP (Pb-free) SSOP – DCT Tape and reel SN74AUC2G125DCTR U25_ _ _ VSSOP – DCU Tape and reel SN74AUC2G125DCUR UM_ (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. (2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site. DCU: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, ⋅ = Pb-free). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar, NanoFree are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 2003–2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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