M37273MFH datasheet(19/130 Pages) RENESAS

Part #	M37273MFH

Description	SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

M37273MFH–XXXSP

MITSUBISHI MICROCOMPUTERS

Rev. 1.0

Priority

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

8.3 INTERRUPTS

Interrupts can be caused by 17 different sources consisting of 4 ex-

ternal, 11 internal, 1 software, and reset. Interrupts are vectored in-

terrupts with priorities as shown in Table 8.3.1. Reset is also included

in the table because its operation is similar to an interrupt.

When an interrupt is accepted,

x The contents of the program counter and processor status regis-

ter are automatically stored into the stack.

➁ The interrupt disable flag I is set to “1” and the corresponding

interrupt request bit is set to “0.”

➂ The jump destination address stored in the vector address enters

the program counter.

Other interrupts are disabled when the interrupt disable flag is set to

“1.”

All interrupts except the BRK instruction interrupt have an interrupt

request bit and an interrupt enable bit. The interrupt request bits are

in interrupt request registers 1 and 2 and the interrupt enable bits are

in interrupt control registers 1 and 2. Figures 8.3.2 to 8.3.6 show the

interrupt-related registers.

Interrupts other than the BRK instruction interrupt and reset are ac-

cepted when the interrupt enable bit is “1,” interrupt request bit is “1,”

and the interrupt disable flag is “0.” The interrupt request bit can be

set to “0” by a program, but not set to “1.” The interrupt enable bit can

be set to “0” and “1” by a program.

Reset is treated as a non-maskable interrupt with the highest priority.

Figure 8.3.1 shows interrupt control.

8.3.1 Interrupt Causes

(1) VSYNC, OSD interrupts

The VSYNC interrupt is an interrupt request synchronized with

the vertical sync signal.

The OSD interrupt occurs after character block display to the

CRT is completed.

(2) INT1 to INT3 external interrupts

The INT1 to INT3 interrupts are external interrupt inputs, the sys-

tem detects that the level of a pin changes from LOW to HIGH or

from HIGH to LOW, and generates an interrupt request. The in-

put active edge can be selected by bits 3 to 5 of the interrupt

input polarity register (address 00DC16) : when this bit is “0,” a

change from LOW to HIGH is detected; when it is “1,” a change

from HIGH to LOW is detected. Note that both bits are cleared to

“0” at reset.

(3) Timers 1 to 4 interrupts

An interrupt is generated by an overflow of timers 1 to 4.

Vector Addresses

FFFF16, FFFE16

FFFD16, FFFC16

FFFB16, FFFA16

FFF916, FFF816

FFF716, FFF616

FFF516, FFF416

FFF316, FFF216

FFF116, FFF016

FFEF16, FFEE16

FFED16, FFEC16

FFEB16, FFEA16

FFE916, FFE816

FFE716, FFE616

FFE516, FFE416

FFE316, FFE216

FFDF16, FFDE16

Interrupt Source

Reset

OSD interrupt

INT1 external interrupt

Data slicer interrupt

Serial I/O interrupt

Timer 4 interrupt

f(XIN)/4096 interrupt

VSYNC interrupt

Timer 3 interrupt

Timer 2 interrupt

Timer 1 interrupt

INT3 external interrupt

INT2 external interrupt

Multi-master I2C-BUS interface interrupt

Timer 5 • 6 interrupt

BRK instruction interrupt

Remarks

Non-maskable

Active edge selectable

Source switch by software (see note)

Non-maskable

Table 8.3.1 Interrupt Vector Addresses and Priority

Note: Switching a source during a program causes an unnecessary interrupt. Therefore, set a source at initializing of program.

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