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HY57V161610D-I Datasheet(PDF) 2 Page - Hynix Semiconductor

Part No. HY57V161610D-I
Description  2 Banks x 512K x 16 Bit Synchronous DRAM
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

HY57V161610D-I Datasheet(HTML) 2 Page - Hynix Semiconductor

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HY57V161610D-I
Rev. 0.3/Mar. 02
2
PIN CONFIGURATION
VSS
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
1
2
3
4
5
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V DD
DQ0
DQ1
V SSQ
DQ2
DQ3
V DDQ
DQ4
DQ5
V SSQ
DQ6
VDDQ
/WE
/CAS
/RAS
/CS
A11
A10
A0
A1
A2
A3
V DD
50pin TSOP II
400mil x 825mil
0.8mm pin pitch
27
26
DQ7
LDQM
VSS
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
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17
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25
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V DD
DQ0
DQ1
V SSQ
DQ2
DQ3
V DDQ
DQ4
DQ5
V SSQ
DQ6
VDDQ
/WE
/CAS
/RAS
/CS
A11
A10
A0
A1
A2
A3
V DD
50pin TSOP II
400mil x 825mil
0.8mm pin pitch
27
26
DQ7
LDQM
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
CLK
Clock
The system clock input. All other inputs are referenced to the SDRAM on the
rising edge of CLK.
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh.
CS
Chip Select
Command input enable or mask except CLK, CKE and DQM
BA
Bank Address
Select either one of banks during both RAS and CAS activity.
A0 ~ A10
Address
Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS, WE
Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation.
Refer function truth table for details
LDQM, UDQM
Data Input/Output Mask
DQM control output buffer in read mode and mask input data in write mode
DQ0 ~ DQ15
Data Input/Output
Multiplexed data input / output pin
VDD/VSS
Power Supply/Ground
Power supply for internal circuit and input buffer
VDDQ/VSSQ
Data Output Power/Ground
Power supply for DQ
NC
No Connection
No connection


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