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CS4391A Datasheet(PDF) 9 Page - Cirrus Logic |
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CS4391A Datasheet(HTML) 9 Page - Cirrus Logic |
9 / 40 page CS4391A DS600PP3 9 SWITCHING CHARACTERISTICS - PCM MODES (Inputs: Logic 0 = 0 V, Logic 1 = VL) Notes: 6. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled. Parameters Symbol Min Typ Max Units Input Sample Rate Fs 4 - 200 kHz LRCK Duty Cycle 45 50 55 % MCLK Duty Cycle 40 50 60 % SCLK Frequency - -MCLK/2 Hz SCLK Frequency (Note 6) - -MCLK/4 Hz SCLK rising to LRCK edge delay tslrd 20 - - ns SCLK rising to LRCK edge setup time tslrs 20 - - ns SDATA valid to SCLK rising setup time tsdlrs 20 - - ns SCLK rising to SDATA hold time tsdh 20 - - ns slrs t slrd t sd lrs t sd h t SD AT A SC LK LR CK Figure 1. Serial Mode Input Timing |
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