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M5M4V64S30ATP-8A Datasheet(PDF) 23 Page - Mitsubishi Electric Semiconductor

Part No. M5M4V64S30ATP-8A
Description  64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
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Manufacturer  MITSUBISHI [Mitsubishi Electric Semiconductor]
Direct Link  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor

M5M4V64S30ATP-8A Datasheet(HTML) 23 Page - Mitsubishi Electric Semiconductor

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MITSUBISHI LSIs
MITSUBISHI ELECTRIC
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
Mar'98
SDRAM (Rev.1.3)
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank . Random column access is al-
lowed. Write recovery time (tWR) is required from the last data to PRE command.
Write Interrupted by Precharge (BL=4)
CLK
Command
A0-9
A10
BA0,1
DQ
Write
Yi
0
00
PRE
0
00
DQM
ACT
Xb
Xb
00
tWR
tRP
A11
Xb
Dai0
Dai1
Dai2
23
[ Write Interrupted by Burst Terminate ]
A burst terminate command TBST can be used to terminate a burst write operation. In this case,
the write recovery time is not required and the bank remains active (Please see the waveforms
below). The WRITE to TBST minimum interval is one CLK.
Write Interrupted by Burst Terminate(BL=4)
CLK
Command
A0-9
A10
BA
DQ
WRITE
Yi
0
0
Dai0
DQMU/DQML
(DQM)
TBST
Dai1
Dai2


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