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M5M4V64S30ATP-8A Datasheet(PDF) 19 Page - Mitsubishi Electric Semiconductor

Part No. M5M4V64S30ATP-8A
Description  64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
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Manufacturer  MITSUBISHI [Mitsubishi Electric Semiconductor]
Direct Link  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor

M5M4V64S30ATP-8A Datasheet(HTML) 19 Page - Mitsubishi Electric Semiconductor

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MITSUBISHI LSIs
MITSUBISHI ELECTRIC
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
Mar'98
SDRAM (Rev.1.3)
BURST INTERRUPTION
[ Read Interrupted by Read ]
Burst read operation can be interrupted by new read of any bank. Random column access is allowed.
READ to READ interval is minimum 1 CLK.
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of any bank. Random column access is allowed. In this
case, the DQ should be controlled adequately by using the DQM to prevent the bus contention. The output
is disabled automatically 1 cycle after WRITE assertion.
Read Interrupted by Read (BL=4, CL=3)
CLK
Command
A0-9
A10
BA0,1
DQ
Yi
Qai0
Qaj1 Qbk0 Qbk1
Qaj0
Qbk2
Qal0
Qal1
Qal2
Qal3
READ READ
READ
READ
Yj
Yk
Yl
0
0
0
0
00
10
00
01
A11
DQM control
Write control
Read Interrupted by Write (BL=4, CL=3)
CLK
Command
A0-9
A10
BA0,1
Q
READ
Yi
0
00
Qai0
Write
Yj
0
00
D
Daj0
Daj1
Daj2
Daj3
DQM
A11
19


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