M5M4V64S30ATP-8A datasheet(12/51 Pages) MITSUBISHI | 64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM

Part No.	M5M4V64S30ATP-8A

Description	64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM

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Manufacturer	MITSUBISHI [Mitsubishi Electric Semiconductor]

Direct Link	http://www.mitsubishichips.com

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MITSUBISHI LSIs

MITSUBISHI ELECTRIC

64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM

M5M4V64S30ATP-8A,-8L,-8, -10L, -10

Mar'98

SDRAM (Rev.1.3)

POWER ON SEQUENCE

Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM

from damaged or malfunctioning.

1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the inputs.

2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200µs.

3. Issue precharge commands for all banks. (PRE or PREA)

4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register.

After these sequence, the SDRAM is idle state and ready for normal operation.

MODE REGISTER

Burst Length, Burst Type and /CAS Latency can be programmed by

setting the mode register (MRS). The mode register stores these data

until the next MRS command, which may be issued when both banks

are in

Å@idle state. After tRSC from a MRS command, the SDRAM is

ready for new command.

R: Reserved for Future Use

BL

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

BURST

LENGTH

BT= 0

BT= 1

1

2

4

8

R

FP

1

2

4

8

R

0

1

BURST

TYPE

SEQUENTIAL

INTERLEAVED

A11 A10 A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

BA1

BA0

0

WM

0

LTMODE

BT

BL

0

CL

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

LATENCY

MODE

/CAS LATENCY

2

3

R

/CS

/RAS

/CAS

/WE

BA0,1 A11-A0

CLK

V

12

FP: Full Page

0

1

WRITE

MODE

BURST

SINGLE BIT

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M5M4V64S30ATP-8A Datasheet(PDF) 12 Page - Mitsubishi Electric Semiconductor

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