M5M4V64S30ATP-8A datasheet(30/51 Pages) MITSUBISHI | 64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM

Part #	M5M4V64S30ATP-8A

Description	64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM

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Manufacturer	MITSUBISHI [Mitsubishi Electric Semiconductor]

Direct Link	http://www.mitsubishichips.com

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MITSUBISHI LSIs

MITSUBISHI ELECTRIC

64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM

M5M4V64S30ATP-8A,-8L,-8, -10L, -10

Mar'98

SDRAM (Rev.1.3)

CLK

Signal

1.4V

Any AC timing is

referenced to the input

signal crossing through

1.4V.

AC TIMING REQUIREMENTS

(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted)

Input Pulse Levels:

0.8V to 2.0V

Input Timing Measurement Level:

1.4V

30

Symbol Parameter

Limits

Unit

note

Min.

Max.

Min.

Max.

Min.

Max.

tCLK

CLK cycle time

CL=2

12

15

ns

CL=3

8

10

ns

tCH

CLK High pulse width

3

ns

tCL

CLK Low pulse width

3

ns

tT

Transition time of CLK

1

10

1

10

ns

tIS

Input Setup time (all inputs)

2

ns

tIH

Input Hold time (all inputs)

1

ns

tRC

Row Cycle time

72

70

ns

tRCD

Row to Column Delay

20

ns

tRAS

Row Active time

48

100K

50

100K

ns

tRP

Row Precharge time

20

ns

tWR

Write Recovery time

10

ns

tRRD

Act to Act Delay time

16

20

ns

2

tCCD

Col to Col Delay time

8

10

ns

tRSC

Mode Register Set

Cycle time

16

20

ns

tSRX

Self Refresh Exit time

8

10

ns

tREF

Refresh Interval time

64

ms

15

10

4

1

3

1

90

30

60

30

10

20

10

20

10

Note:1

The timing requirements are assumed tT=1ns. If tT is longer than 1ns, (tT-1)ns should be

added to the parameter.

2

2 ACT commands are allowed within tRC.

1

-8A

-10L, -10

-8L,-8

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M5M4V64S30ATP-8A Datasheet(PDF) 30 Page - Mitsubishi Electric Semiconductor

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