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ADSP-TS202S Datasheet(PDF) 3 Page - Analog Devices

Part No. ADSP-TS202S
Description  TigerSHARC Embedded Processor
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADSP-TS202S Datasheet(HTML) 3 Page - Analog Devices

 
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ADSP-TS202S
Preliminary Technical Data
Rev. PrB
|
Page 3 of 40
|
December 2003
GENERAL DESCRIPTION
The ADSP-TS202S TigerSHARC processor is an ultra-high per-
formance, static superscalar processor optimized for large signal
processing tasks and communications infrastructure. The DSP
combines very wide memory widths with dual computation
blocks—supporting 32- and 40-bit floating-point and support-
ing 8-, 16-, 32-, and 64-bit fixed-point processing—to set a new
standard of performance for digital signal processors. The
TigerSHARC static superscalar architecture lets the DSP exe-
cute up to four instructions each cycle, performing twenty-four
16-bit fixed-point operations or six floating-point operations.
Four independent 128-bit wide internal data buses, each con-
necting to the six 2M bit memory banks, enable quad-word
data, instruction, and I/O accesses and provide 28G bytes per
second of internal memory bandwidth. Operating at 500 MHz,
the ADSP-TS202S processor’s core has a 2.0 ns instruction cycle
time. Using its Single-Instruction, Multiple-Data (SIMD) fea-
tures, the ADSP-TS202S processor can perform four billion 40-
bit MACs or one billion 80-bit MACs per second. Table 1 shows
the DSP’s performance benchmarks.
The ADSP-TS202S processor is code-compatible with the other
TigerSHARC processors.
The Functional Block Diagram on page 1 shows the ADSP-
TS202S processor’s architectural blocks. These blocks include:
• Dual compute blocks, each consisting of an ALU, multi-
plier, 64-bit shifter, and 32-word register file and associated
Data Alignment Buffers (DABs)
• Dual integer ALUs (IALUs), each with its own 31-word
register file for data addressing and a status register
• A program sequencer with Instruction Alignment Buffer
(IAB) and Branch Target Buffer (BTB)
• An interrupt controller that supports hardware and soft-
ware interrupts, supports level- or edge-triggers, and
supports prioritized, nested interrupts
• Four 128-bit internal data buses, each connecting to the six
2M bit memory banks
• On-chip DRAM (12M bit)
• An external port that provides the interface to host proces-
sors, multiprocessing space (DSPs), off-chip memory-
mapped peripherals, and external SRAM and SDRAM
• A 14 channel DMA controller
• Four full-duplex LVDS link ports
• Two 64-bit interval timers and timer expired pin
• A 1149.1 IEEE compliant JTAG test access port for on-chip
emulation
Figure 2 on page 3 shows a typical single-processor system with
external SRAM and SDRAM. Figure 4 on page 8 shows a typical
multiprocessor system.
The TigerSHARC DSP uses a Static Superscalar* architecture.
This architecture is superscalar in that the ADSP-TS202S pro-
cessor’s core can execute simultaneously from one to four 32-bit
instructions encoded in a Very Large Instruction Word (VLIW)
instruction line using the DSP’s dual compute blocks. Because
Table 1. General Purpose Algorithm Benchmarks
at 500 MHz
Benchmark
Speed
Clock
Cycles
32-bit Algorithm, one billion MACs/s peak performance
1K Point Complex FFT1(Radix2)
1 Cache preloaded
18.8 µs
9419
64K Point Complex FFT1(Radix 2)
2.8 ms
1397544
FIR Filter (per real tap)
1 ns
0.5
[8 × 8][8 × 8] Matrix Multiply (Complex,
Floating-point)
2.8 µs
1399
16-bit Algorithm, four billion MACs/s peak performance
256 Point Complex FFT1 (Radix 2)
1.9 µs
928
I/O DMA Transfer Rate
External port
1G bytes/s
n/a
Link ports (each)
1G bytes/s
n/a
Figure 2. ADSP-TS202S Single-Processor System With External SDRAM
* Static Superscalar™ is a trademark of Analog Devices, Inc.
BOFF
CONTROLIMP1–0
DMAR3–0
HBG
HBR
DMA DEVICE
(OPTIONAL)
DATA
MSH
FLAG3–0
ID2–0
IOEN
RAS
CAS
LDQM
HDQM
SDWE
SDCKE
SDA10
IRQ3–0
SCLK
SCLKRAT2–0
SCLK_VREF
VREF
TMR0E
BM
MSSD3–0
BUSLOCK
SDRAM
MEMORY
(OPTIONAL)
CS
RAS
CAS
DQM
WE
CKE
A10
ADDR
DATA
CLK
POR_IN
JTAG
ADSP-TS202S
BMS
CLOCK
LINK
DEVICES
(4 MAX)
(OPTIONAL)
BOOT
EPROM
(OPTIONAL)
ADDR
MEMORY
(OPTIONAL)
OE
DATA
ADDR
DATA
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
ACK
BR7–0
CPA
MS1–0
DATA63–0
DATA
ADDR
CS
ACK
WE
ADDR31–0
BRST
REFERENCE
RD
WRH/WRL
DPA
DS2–0
CS
LxCLKINP/N
LxACKO
LxDATI3–0P/N
LxBCMPI
LxBCMPO
LxDATO3–0P/N
LxCLKOUTP/N
LxACKI
IORD
IOWR
RST_OUT
RST_IN
REFERENCE


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