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ADSP-TS202S Datasheet(PDF) 6 Page - Analog Devices

Part No. ADSP-TS202S
Description  TigerSHARC Embedded Processor
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADSP-TS202S Datasheet(HTML) 6 Page - Analog Devices

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Rev. PrB
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Page 6 of 40
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December 2003
ADSP-TS202S
Preliminary Technical Data
The external bus can be configured for 32- or 64-bit, little-
endian operations. When the system bus is configured for 64-bit
operations, the lower 32 bits of the external data bus connect to
even addresses, and the upper 32 bits connect to odd addresses.
The external port supports pipelined, slow, and SDRAM proto-
cols. Addressing of external memory devices and memory-
mapped peripherals is facilitated by on-chip decoding of high-
order address lines to generate memory bank select signals.
The ADSP-TS202S processor provides programmable memory,
pipeline depth, and idle cycle for synchronous accesses, and
external acknowledge controls to support interfacing to pipe-
lined or slow devices, host processors, and other memory-
mapped peripherals with variable access, hold, and disable time
requirements.
Host Interface
The ADSP-TS202S processor provides an easy and configurable
interface between its external bus and host processors through
the external port. To accommodate a variety of host processors,
the host interface supports pipelined or slow protocols for
ADSP-TS202S processor accesses of the host as slave or pipe-
lined for host accesses of the ADSP-TS202S processor as slave.
Each protocol has programmable transmission parameters,
such as idle cycles, pipe depth, and internal wait cycles.
The host interface supports burst transactions initiated by a host
processor. After the host issues the starting address of the burst
and asserts the BRST signal, the DSP increments the address
internally while the host continues to assert BRST.
The host interface provides a deadlock recovery mechanism that
enables a host to recover from deadlock situations involving the
DSP. The BOFF signal provides the deadlock recovery mecha-
Figure 3. ADSP-TS202S Memory Map
RESERVED
RESERVED
INTERNAL REGISTERS (UREG S)
INTERNAL MEMO RY BLOCK 4
INTERNAL MEMORY BLOCK 2
INTERNAL MEMORY BLOCK 0
0x03FFFFFF
0X001E0000
0x001E03FF
0x000CFFFF
0x000C0000
0x0008FFFF
0x00080000
0x0004FFFF
0x00040000
0x0000FFFF
0x00000000
INTERNAL SPACE
PROCESSO R ID 7
PROCESSO R ID 6
PROCESSO R ID 5
PROCESSO R ID 4
PROCESSO R ID 3
PROCESSO R ID 2
PROCESSO R ID 1
PROCESSO R ID 0
BROADCAST
HOST (
MSH)
BANK 1 (
MS1)
BANK 0 (
MS0)
MSSD BANK 0 (
MSSD0)
INTERNAL MEMORY
0x50000000
0x40000000
0x38000000
0x30000000
0x2C000000
0x28000000
0x24000000
0x20000000
0x1C000000
0x18000000
0x14000000
0x10000000
0X0C000000
0x03FFFFFF
0x00000000
GLOBAL SPACE
0xFFFFFFFF
EACH IS A COPY
OF INTERNAL SPACE
RESERVED
INTERNAL MEMO RY BLOCK 6
INTERNAL MEMO RY BLOCK 8
0x0010FFFF
0x00100000
INTERNAL MEMO RY BL OCK 10
0x0014FFFF
0x00140000
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
SOC REGISTERS (UREGS)
0X001F0000
0x001F03FF
MSSD BANK 1 (
MSSD1)
MSSD BANK 2 (
MSSD2)
MSSD BANK 3 (
MSSD3)
0x60000000
0x70000000
0x80000000
RESERVED
RESERVED
RESERVED
RESERVED
0x54000000
0x44000000
0x64000000
0x74000000


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