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IN74HCT109 Datasheet(PDF) 1 Page - Integral Corp.

Part No. IN74HCT109
Description  DUAL J-K FLIP-FLOP WITH SET AND RESET
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Maker  INTEGRAL [Integral Corp.]
Homepage  http://www.iksemi.com/
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IN74HCT109 Datasheet(HTML) 1 Page - Integral Corp.

   
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IN74HCT109
1
DUAL J-K FLIP-FLOP
WITH SET AND
RESET
High-Performance Silicon-Gate CMOS
The IN74HCT109 is identical in pinout to the LS/ALS109. The
IN74HCT109 may be used as a level converter for interfacing
TTL or NMOS outputs to High Speed CMOS inputs.
This device consists of two J- K flip-flops with individual set,
reset, and clock inputs. Changes at the inputs are reflected at the
outputs with the next low-to-high transition of the clock. Both Q to
Q outputs are available from each flip-flop.
• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
ORDERING INFORMATION
IN74HCT109N Plastic
IN74HCT109D SOIC
TA = -55° to 125° C for all
packages.
FUNCTION TABLE
Inputs
Output
Set
Reset
Clock
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H
*
H
*
H
H
L
L
L
H
H
H
H
L
Toggle
H
H
L
H
No
Change
H
H
H
H
H
L
H
H
L
X
X
No
Change
X = Don’t care
*Both outputs will remain high as long as
Set and Reset are low., but the output
states are unpredictable if Set and Reset
go high simultaneously.
LOGIC DIAGRAM
PIN 16=VCC
PIN 8 = GND
PIN ASSIGNMENT


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