M5M4V64S20ATP-8 datasheet(2/48 Pages) MITSUBISHI | 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM

Part No.	M5M4V64S20ATP-8

Description	64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM

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Manufacturer	MITSUBISHI [Mitsubishi Electric Semiconductor]

Direct Link	http://www.mitsubishichips.com

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M5M4V64S20ATP-8, -10, -12

Jan'97

Preliminary

MITSUBISHI LSIs

64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM

MITSUBISHI ELECTRIC

SDRAM (Rev.0.2)

BLOCK DIAGRAM

Address Buffer

A0-11 BA0,1

Control Signal Buffer

/CS /RAS /CAS /WE DQM

CLK

CKE

Clock Buffer

Memory Array

Bank #0

Control Circuitry

I/O Buffer

DQ0-7(0-3)

Mode

Register

Memory Array

Bank #1

Memory Array

Bank #2

Memory Array

Bank #3

Type Designation Code

M 5M 4 V 64 S 3 0 A TP - 8

Cycle Time (min.) 8: 8ns, 10: 10ns, 12: 12ns

Package Type TP: TSOP(II)

Process Generation

Function 0: Random Column, 1: 2N-rule

Organization 2n 2: x4, 3: x8, 4: x16

Synchronous DRAM

Density 64:64M bits

Interface S: SSTL, V:LVTTL

Memory Style (DRAM)

Use, Recommended Operating Conditions, etc

Mitsubishi Main Designation

This rule is applied to only Synchronous DRAM family.

2

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M5M4V64S20ATP-8 Datasheet(PDF) 2 Page - Mitsubishi Electric Semiconductor

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