M5M4V64S20ATP-8 datasheet(16/48 Pages) MITSUBISHI

Part #	M5M4V64S20ATP-8

Description	64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM

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Manufacturer	MITSUBISHI [Mitsubishi Electric Semiconductor]

Direct Link	http://www.mitsubishichips.com

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16 / 48 page

M5M4V64S20ATP-8, -10, -12

Jan'97

Preliminary

MITSUBISHI LSIs

64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM

MITSUBISHI ELECTRIC

SDRAM (Rev.0.2)

WRITE

After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set at the same

cycle as the WRITE. Following (BL -1) data are written into the RAM, when the Burst Length is BL. The

start address is specified by A8-0 (x 8) / A9-0 (x 4), and the address sequence of burst data is defined by the

Burst Type. A WRITE command may be applied to any active bank, so the row precharge time (tRP) can be

hidden behind continuous input data by interleaving the multiple banks. From the last input data to the PRE

command, the write recovery time (tWR) is required. When A10 is high at a WRITE command, the auto-

precharge (WRITEA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhib-

ited till the internal precharge is complete. The internal precharge begins at tWR after the last input data

cycle. The next ACT command can be issued after tRP from the internal precharge timing.

Multi Bank Interleaving WRITE (BL=4)

CLK

Command

A0-9

A10

BA0,1

DQ

ACT

Xa

00

Write

Y

00

Write

Y

0

10

Da0

ACT

Xb

10

0

10

tRCD

PRE

Xa

A11

Xa

Xb

0

Xa

0

00

PRE

0

Da1

Da2

Da3

Db0

Db1

Db2

Db3

WRITE with Auto-Precharge (BL=4)

tWR

CLK

Command

A0-9

A10

BA0,1

DQ

ACT

Xa

00

Write

Y

1

00

Da0

Da1

Da2

Da3

ACT

Xa

00

Internal precharge starts

tRCD

tRP

A11

Xa

16

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