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K9F2808U0C-PIB0 Datasheet(PDF) 10 Page - Samsung semiconductor

Part # K9F2808U0C-PIB0
Description  16M x 8 Bit NAND Flash Memory
Download  31 Pages
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Manufacturer  SAMSUNG [Samsung semiconductor]
Direct Link  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

K9F2808U0C-PIB0 Datasheet(HTML) 10 Page - Samsung semiconductor

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FLASH MEMORY
10
K9F2808U0C
CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz)
NOTE : Capacitance is periodically sampled and not 100% tested.
Item
Symbol
Test Condition
Min
Max
Unit
Input/Output Capacitance
CI/O
VIL=0V
-
10
pF
Input Capacitance
CIN
VIN=0V
-
10
pF
VALID BLOCK
NOTE :
1. The
device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-
sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits
. Do not erase or program
factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase
cycles.
3. Minimum 502 valid blocks are guaranteed for each contiguous 64Mb memory space.
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
NVB
1004
-
1024
Blocks
Program/Erase Characteristics
NOTE : Typical program time is defined as the time within which more than 50% of the whole pages are programmed at Vcc of 3.3V and temperature of
25
°C .
Parameter
Symbol
Min
Typ
Max
Unit
Program Time
tPROG
-
200
500
µs
Number of Partial Program Cycles
in the Same Page
Main Array
Nop
--
2
cycles
Spare Array
-
-
3
cycles
Block Erase Time
tBERS
-2
3
ms
AC TEST CONDITION
(K9F2808U0C-XCB0 :TA=0 to 70
°C, K9F2808U0C-XIB0:TA=-40 to 85°C
K9F2808U0C : Vcc=2.7V~3.6V unless otherwise noted)
Parameter
K9F2808U0C
Input Pulse Levels
0.4V to 2.4V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load (VccQ:3.0V +/-10%)
1 TTL GATE and CL=50pF
Output Load (VccQ:3.3V +/-10%)
1 TTL GATE and CL=100pF
MODE SELECTION
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
CLE
ALE
CE
WE
RE
GND
WP
Mode
HL
L
H
X
X
Read Mode
Command Input
L
H
L
H
X
X
Address Input(3clock)
HL
L
H
X
H
Write Mode
Command Input
L
H
L
H
X
H
Address Input(3clock)
L
L
L
H
L
H
Data Input
L
L
L
H
L
X
Data Output
LL
L
H
H
L
X
During Read(Busy)
XX
X
X
H
L
X
During Read(Busy)
X
X
X
X
X
L
H
During Program(Busy)
X
X
X
X
X
X
H
During Erase(Busy)
X
X(1)
X
X
X
X
L
Write Protect
XX
H
X
X
0V
0V/VCC(2) Stand-by


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