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KS57P0504 Datasheet(PDF) 28 Page - Samsung semiconductor |
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KS57P0504 Datasheet(HTML) 28 Page - Samsung semiconductor |
28 / 282 page ADDRESS SPACES KS57C0502/C0504/P0504 MICROCONTROLLER 2–16 PROGRAM COUNTER (PC) A 12-bit program counter (PC) stores addresses for instruction fetches during program execution. Whenever a reset operation or an interrupt occurs, bits PC11 through PC0 are set to the vector address. Bit PC12–PC13 is re- served to support future expansion of the device's ROM size. Usually, the PC is incremented by the number of bytes of the instruction being fetched. One exception is the 1-byte REF instruction which is used to reference instructions stored in the ROM. PROGRAM STATUS WORD (PSW) The program status word (PSW) is an 8-bit word, mapped to RAM locations FB0H–FB1H, that defines system status and program execution status and which permits an interrupted process to resume operation after an inter- rupt request has been serviced. PSW values are mapped as follows: FB0H IS1 IS0 EMB ERB FB1H C SC2 SC1 SC0 The PSW can be manipulated by 1-bit or 4-bit read/write and by 8-bit read instructions, depending on the spe- cific bit or bits being addressed. The PSW can be addressed during program execution regardless of the current value of the enable memory bank (EMB) flag. Part or all of the PSW is saved to stack prior to execution of a subroutine call or hardware interrupt. After the interrupt has been processed, the PSW values are popped from the stack back to the PSW address. When a RESET is generated, the EMB and ERB values are set according to the RESET vector address, and the carry flag is left undefined (or the current value is retained). PSW bits IS0, IS1, SC0, SC1, and SC2 are all cleared to logic zero. Table 2–5. Program Status Word Bit Descriptions PSW Bit Identifier Description Bit Addressing Read/Write IS1, IS0 Interrupt status flags 1, 4 R/W EMB Enable memory bank flag 1 R/W ERB Enable register bank flag 1 R/W C Carry flag 1 R/W SC2, SC1, SC0 Program skip flags 8 R |
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