AD9945

–13–

24

REFB

23

REFT

22

CCDIN

21

AVSS

D2

1

D3

2

D4

3

20

AVDD

19

SHD

18

SHP

17

CLPOB

D5

4

D6

5

D7

6

D8

7

D9

8

DATA

OUTPUTS

12

3V

DRIVER

SUPPLY

3V

ANALOG

SUPPLY

5

CLOCK

INPUTS

3

SERIAL

INTERFACE

3V

ANALOG

SUPPLY

CCDIN

PIN 1

IDENTIFIER

AD9945

(Not to Scale)

TOP VIEW

1.0 F

0.1 F

0.1 F

0.1 F

0.1 F

D0

D1

NC = NO CONNECT

1.0 F

NOTE

THE EXPOSED PAD ON THE BOTTOM OF THE AD9945 SHOULD BE

SOLDERED TO THE GND PLANE OF THE PRINTED CIRCUIT BOARD

Figure 11. Recommended Circuit Configuration for CCD Mode

REV.

C

Internal Power-On Reset Circuitry

After power-on, the AD9945 will automatically reset all internal

registers and perform internal calibration procedures. This takes

approximately 1 ms to complete. During this time, normal clock

signals and serial write operations may occur. However, serial

register writes will be ignored until the internal reset operation

is completed.

Required Start-Up Write

During power-up of the AD9945, 0x838 must be written into

Register 0xD for proper start-up operation.

Grounding and Decoupling Recommendations

As shown in Figure 11, a single ground plane is recommended for

the AD9945. This ground plane should be as continuous as

possible. This will ensure that all analog decoupling capacitors

provide the lowest possible impedance path between the power

and bypass pins and their respective ground pins. All decoupling

capacitors should be located as close as possible to the package

pins. A single clean power supply is recommended for the AD9945,

but a separate digital driver supply may be used for DRVDD

(Pin 11). DRVDD should always be decoupled to DRVSS (Pin 12),

which should be connected to the analog ground plane. If the digital

outputs (Pins 1 to 10, 31, and 32) must drive a load larger than 20 pF,

buffering is recommended to reduce digital code transition noise.

Alternatively, placing series resistors close to the digital output pins

may also help reduce noise.