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CD54HC4017 Datasheet(PDF) 6 Page - Texas Instruments |
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CD54HC4017 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 14 page 
6 FIGURE 3. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS Timing Diagrams FIGURE 4. FIGURE 5. Test Circuits and Waveforms (Continued) trCL tfCL GND VCC GND VCC 50% 90% 10% GND CLOCK INPUT DATA INPUT OUTPUT SET, RESET OR PRESET VCC 50% 50% 90% 10% 50% 90% tREM tPLH tSU(H) tTLH tTHL tH(L) tPHL IC CL 50pF tSU(L) tH(H) CL CL P N P N PN P N D CL Q C FF DETAIL CL CL CL CL CL CL Q R CLOCK MASTER RESET CLOCK ENABLE “0” “1” “2” “3” “4” “5” “6” “7” “8” “9” TERMINAL COUNT 0 1 2 3 4 5 6 7 8 9 0 1 2 CD54HC4017, CD74HC4017 |
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