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CD54HC4017 Datasheet(PDF) 5 Page - Texas Instruments

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Part No. CD54HC4017
Description  High-Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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CD54HC4017 Datasheet(HTML) 5 Page - Texas Instruments

 
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5
MR to any Dec. Out
tPLH,
tPHL
CL = 50pF
2
-
-
230
-
290
-
345
ns
CL = 50pF
4.5
-
-
46
-
58
-
69
ns
CL = 15pF
5
-
19
-
-
-
-
-
ns
CL = 50pF
6
-
-
39
-
49
-
59
ns
MR to TC
tPLH,
tPHL
CL = 50pF
2
-
-
230
-
290
-
345
ns
CL = 50pF
4.5
-
-
46
-
58
-
69
ns
CL = 15pF
5
-
19
-
-
-
-
-
ns
CL = 50pF
6
-
-
39
-
49
-
59
ns
Transition Time TC, Dec. Out
tTLH,tTHL
CL = 50pF
2
-
-
75
-
95
-
110
ns
CL = 50pF
4.5
-
-
15
-
19
-
22
ns
CL = 50pF
6
-
-
13
-
16
-
19
ns
Input Capacitance
CIN
CL = 50pF
-
-
-
10
-
10
-
10
pF
Maximum CP Frequency
fMAX
CL = 15pF
5
-
60
-
-
-
-
-
MHz
Power Dissipation Capacitance
(Notes 2, 3)
CPD
CL = 15pF
5
-
39
-
-
-
-
-
pF
NOTES:
2. CPD is used to determine the dynamic power consumption, per package.
3. PD = VCC
2 f
i Σ€ CL VCC
2 fo where f
i = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage.
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
VCC
(V)
25oC
-40oC TO
85oC
-55oC TO 125oC
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
Test Circuits and Waveforms
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 2. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
CLOCK
90%
50%
10%
GND
VCC
trCL
tfCL
50%
50%
tWL
tWH
10%
tWL + tWH =
fCL
I
tPHL
tPLH
tTHL
tTLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
VCC
tr = 6ns
tf = 6ns
90%
CD54HC4017, CD74HC4017


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