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ADV202BBCZ-150 Datasheet(PDF) 35 Page - Analog Devices |
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ADV202BBCZ-150 Datasheet(HTML) 35 Page - Analog Devices |
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35 / 40 page  ADV202 Rev. 0 | Page 35 of 40 DECODE—MULTICHIP MASTER/SLAVE In a master/slave configuration, it is expected that the master HVF outputs are connected to the slave HVF inputs and that each SCOMM[5] pin is connected to the same GPIO on the host. In a slave/slave configuration, the common HVF for both ADV202s is generated by an external house sync and each SCOMM[5] is connected to the same GPIO output on the host. SWIRQ1, Software Interrupt 1 in the EIRQIE register, must be unmasked on both devices to enable multichip mode. DATA[31:0] HDATA[31:0] ADDR[3:0] ADDR[3:0] CS CS RD RD WR WE ACK ACK IRQ CS RD WR ACK IRQ DREQ DACK IRQ DREQ DREQ FIELD VSYNC HSYNC DACK DACK G I/O SCOMM[5] VCLK 1080i VIDEO OUT MCLK VDATA[11:2] 32-BIT HOST CPU ADV730xA 10-BIT SD/HD VIDEO DECODER ADV202 _1_MASTER SCOMM[5] HDATA[31:0] ADDR[3:0] CS RD WE ACK IRQ FIELD VSYNC HSYNC DREQ DACK VCLK MCLK VDATA[11:2] ADV202 _2_SLAVE CLKIN Y[9:0] C[9:0] CbCr CbCr YY 74.25MHz OSC Figure 26. Decode —Multichip Master/Slave Application DIGITAL STILL CAMERA/CAMCORDER Figure 27 is a typical configuration for a digital camera or camcorder. D[9:0] 10 DATA INPUTS[9:0] MCLK VCLK VFRM VRDY VSTRB VDATA[11:2] SDATA SERIAL DATA SCK SERIAL CLK SL SERIAL EN AD9843A FPGA 16-BIT HOST CPU ADV202 DATA[15:0] HDATA[15:0] ADDR[3:0] ADDR[3:0] CS CS RD RD WE WE ACK ACK IRQ IRQ Figure 27. Digital Still Camera/Camcorder Application |
Similar Part No. - ADV202BBCZ-150 |
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Similar Description - ADV202BBCZ-150 |
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