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HY5DU12422CLTP-X Datasheet(PDF) 24 Page - Hynix Semiconductor

Part # HY5DU12422CLTP-X
Description  512Mb DDR SDRAM
Download  31 Pages
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

HY5DU12422CLTP-X Datasheet(HTML) 24 Page - Hynix Semiconductor

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Rev. 1.0 / Mar. 2005
24
1
HY5DU12422C(L)TP
HY5DU12822C(L)TP
HY5DU121622C(L)TP
AC CHARACTERISTICS (note: 1 - 9 / AC operating conditions unless otherwise noted)
Parameter
Symbol
DDR400B
DDR333
DDR266A
DDR266B
DDR200
UNIT
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Row Cycle Time
tRC
55
-
60
-
65
-
65
-
70
-
ns
Auto Refresh Row
Cycle Time
tRFC
70
-
72
-
75
-
75
-
80
-
ns
Row Active Time
tRAS
40
70K
42
70K
45
120K
45
120K
50
120K
ns
Active to Read with
Auto Precharge Delay
tRAP
tRCD or
tRASmin
-
tRCD or
tRASmin
-
tRCD or
tRASmin
-
tRCD or
tRASmin
-
tRCD or
tRASmin
-ns
Row Address to
Column Address Delay
tRCD
15
-
18
-
20
-
20
-
20
-
ns
Row Active to Row
Active Delay
tRRD
10
-
12
-
15
-
15
-
15
-
ns
Column Address to
Column Address Delay
tCCD
1-
1
-
1
-
1-
1
-
tCK
Row Precharge Time
tRP
15
-
18
-
20
-
20
-
20
-
ns
Write Recovery Time
tWR
15
-
15
-
15
-
15
-
15
-
ns
Internal Write to Read
Command Delay
tWTR
2-
1
-
1
-
1-
1
-
tCK
Auto Precharge Write
Recovery + Precharge
Time22
tDAL
(tWR/
tCK)
+
(tRP/tCK)
-
(tWR/
tCK)
+
(tRP/tCK)
-
(tWR/
tCK)
+
(tRP/tCK)
-
(tWR/
tCK)
+
(tRP/tCK)
-
(tWR/
tCK)
+
(tRP/tCK)
-tCK
System
Clock Cycle
Time24
CL = 3
tCK
5
10
-
-
-
-
---
-
CL = 2.5
-
-
6
12
7.5
12
7.5
12
8.0
12
ns
CL = 2
-
-
7.5
12
7.5
121012
10
12
ns
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Data-Out edge to Clock
edge Skew
tAC
-0.7
0.7
-0.7
0.7
-0.75
0.75
-0.75
0.75
-0.75
0.75
ns
DQS-Out edge to Clock
edge Skew
tDQSCK
-0.55
0.55
-0.6
0.6
-0.75
0.75
-0.75
0.75
-0.75
0.75
ns
DQS-Out edge to Data-
Out edge Skew21
tDQSQ
-
0.4
-
0.45
-
0.5
-
0.5
-
0.6
ns
Data-Out hold time
from DQS20
tQH
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-ns
Clock Half Period19,20
tHP
min
(tCL,tCH)
-
min
(tCL,tCH)
-
min
(tCL,tCH)
-
min
(tCL,tCH)
-
min
(tCL,tCH)
-ns
Data Hold Skew
Factor20
tQHS
-
0.5
-
0.55
-
0.75
-
0.75
-
0.75
ns
Valid Data Output
Window
tDV
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
ns


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