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HY5DU12422CTP Datasheet(PDF) 3 Page - Hynix Semiconductor

Part # HY5DU12422CTP
Description  512Mb DDR SDRAM
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

HY5DU12422CTP Datasheet(HTML) 3 Page - Hynix Semiconductor

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Rev. 1.0 / Mar. 2005
3
1
HY5DU12422C(L)TP
HY5DU12822C(L)TP
HY5DU121622C(L)TP
DESCRIPTION
The HY5DU12422C(L)TP, HY5DU12822C(L)TP and HY5DU121622C(L)TP are a 536,870,912-bit CMOS Double Data
Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density
and high bandwidth.
This Hynix 512Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
•VDD, VDDQ = 2.5V ± 0.2V for DDR200, 266, 333
VDD, VDDQ = 2.6V ± 0.1V for DDR400
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
x16 device has two bytewide data strobes (UDQS,
LDQS) per each x8 I/O
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
On chip DLL align DQ and DQS transition with CK
transition
DM mask write data-in at the both rising and falling
edges of the data strobe
All addresses and control inputs except data, data
strobes and data masks latched on the rising edges
of the clock
Programmable CAS latency 2/2.5 (DDR200, 266,
333) and 3 (DDR400) supported
Programmable burst length 2 / 4 / 8 with both
sequential and interleave mode
Internal four bank operations with single pulsed
/RAS
Auto refresh and self refresh supported
tRAS lock out function supported
8192 refresh cycles / 64ms
JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch
Lead free (ROHS* Compliant)
ORDERING INFORMATION
* X means speed grade
Part No.
Configuration
Package
HY5DU12422C(L)TP-X*
128M x 4
400mil
66pin
TSOP-II
(Lead free)
HY5DU12822C(L)TP-X*
64M x 8
HY5DU121622C(L)TP-X*
32M x 16
OPERATING FREQUENCY
Grade
Clock Rate
Remark
(CL-tRCD-tRP)
-D43
200MHz@CL3
DDR400B (3-3-3)
- J
133MHz@CL2
166MHz@CL2.5
DDR333 (2.5-3-3)
- K
133MHz@CL2
133MHz@CL2.5
DDR266A (2-3-3)
- H
100MHz@CL2
133MHz@CL2.5
DDR266B (2.5-3-3)
- L
100MHz@CL2
DDR200 (2-2-2)
*ROHS (Restriction Of Hazardous Substance)


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