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MAX5855 Datasheet(PDF) 43 Page - Maxim Integrated Products

Part No. MAX5855
Description  16-Bit, 4.9Gsps Wideband Interpolating and Modulating RF DAC with JESD204B Interface
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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MAX5855 Datasheet(HTML) 43 Page - Maxim Integrated Products

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OFF-CHIP DAC CLOCK SOURCE
AND SYSTEM CLOCK GENERATION
RF DAC
CLOCK GENERATION
DACCLK /
DEVICE CLOCK
RCLKP/N
EQUALIZATION
CDR
SERIAL TO PARALLEL
20b
RX LINK LAYER
10/8B DECODING
ALIGNMENT
SAMPLE ASSEMBLY
DSP
NCO
DPx
DNx
16b
14b
DACCLK
clk_fx
PLL
CLKP/N
OUTP
OUTN
FRAME CLOCK
SYNC~
GENERATION
SYNCNP/N
DIV
1/2/4
CfgChipOM.RclkM1-0
CfgClkDiv.
RDIV3-0
CfgCMU1.
Cref_divsel1-0
RCLKi
FCLK
CfgClkDiv.
PCLKS1-0
PCLK
RCLKi
PCLK
PCLK is used to program the registers at address 0x0400-0x0DFF
FCLK
FCLK is the JESD frame clock divide down from DACCLK
RCLK
RCLK is internal PLL reference clock as well as used by external FPGA,
and derived from DACCLK
CLOCK
MANAGEMENT
UNIT
DIV
1/2/4
Figure 27. MAX5855 Clock Subsystem
The DAC output signal phase noise and jitter will mostly be determined by the on-chip PLL performance. The reference
clock phase noise will dominate within the 100kHz PLL loop bandwidth. In that frequency range the input clock phase
noise will be amplified by 20 x log(FDAC/FREF).
DAC Clock PLL
The MAX5855 differential high-frequency clock input (CLKP/CLKN) accepts an external reference clock signal that is
multiplied internally by a phase-locked-loop (PLL). The PLL includes user-programmable multiplication factors which
provide flexibility in the reference clock selection. Figure 28 shows the functional block diagram of the PLL.
PHASE/
FREQUENCY
DETECTOR (PFD)
REFERENCE
DIVIDER
(1/2/4)
VCO/FEEDBACK
DIVIDER
(/20)
CHARGE
PUMP
POST DIVIDER
(/1)
DUAL
BAND
VCO
LOOP
FILTER
(EXTERNAL)
DACCLK
EXTERNAL
REFERENCE
CLOCK
Figure 28. DAC Clock PLL Functional Block Diagram
MAX5855
16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com
Maxim Integrated | 43


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