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MAX5855 Datasheet(PDF) 35 Page - Maxim Integrated Products

Part No. MAX5855
Description  16-Bit, 4.9Gsps Wideband Interpolating and Modulating RF DAC with JESD204B Interface
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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MAX5855 Datasheet(HTML) 35 Page - Maxim Integrated Products

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Table 3. Status Register Bits (continued)
RLaneRegs0-4.StatRlane.FChkErr
Latched, ILA sequence FCHK error detected on Lane N
RLaneRegs0-4.StatRlane.LCfgErr
Latched, ILA sequence lane configuration error detected on Lane N
RLaneRegs0-4.StatRlane.ILAerr
Latched, ILA sequence decode (/R/, /Q/, /A/ character) error detected on Lane N
RLinkRegs.StatRlinkILA.ILAnsync
Real-time, ILA synchronization not achieved
RLinkRegs.StatRlinkILA.ILAfailure
Latched, ILA failed, indicates that at least one FIFO in a JESD lane overflowed before the
FIFO reads started.
RLinkRegs.StatRlinkPRBS.PRBSerr1 Latched, Converter 2 (Q-sample) PRBS error detected
RLinkRegs.StatRlinkPRBS.PRBSerr0 Latched, Converter 1 (I-sample) PRBS error detected
RLinkRegs.StatRlinkSTP.STPerr1
Latched, Converter 2 (Q-sample) short test pattern error detected
RLinkRegs.StatRlinkSTP.STPerr0
Latched, Converter 1 (I-sample) short test pattern error detected
Digital Control Pins
The MAX5855 contains two 1.8V CMOS logic input control pins: RESETB and MUTE. The device is placed in a reset
state when RESETB is logic-low. On power-up, RESETB should remain low until all supply voltages have stabilized and
an external clock is applied to CLKP/CLKN.
The MUTE pin and the register-based MUTE control when the device enters the mute mode. In mute mode, the DAC
digital input is set to mid-scale. A logic-high on the MUTE pin will place the device into mute mode while a logic-low may
allow normal operation. The main purpose of MUTE pin is to eliminate any transmit power during the receive time of
a TDMA system while the purpose of the MUTE bit is to protect the system PA during startup or error conditions. The
register-based mute can be configured through the serial interface enabling the mute mode internally regardless of the
state of the MUTE pin. Similar to the interrupt mask registers, there are mute enable registers which generate the internal
mute signal under defined conditions. Table 3 shows all the status register bits that can be used to generate the internal
mute. The states of all registers in the device are preserved while the RF DAC output is muted.
DAC
MUTE
MUTE_PIN
JESD204B STATUS REGISTERS (5)
JESD204B MUTE ENABLE (5)
DSP STATUS REGISTER
DSP EMUTE REGISTER
BIT-WISE
AND
BIT-WISE
AND
7
0
7
0
Figure 20. Mute Generation Logic
MAX5855
16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com
Maxim Integrated | 35


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