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MAX5855 Datasheet(PDF) 21 Page - Maxim Integrated Products

Part No. MAX5855
Description  16-Bit, 4.9Gsps Wideband Interpolating and Modulating RF DAC with JESD204B Interface
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com

MAX5855 Datasheet(HTML) 21 Page - Maxim Integrated Products

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Detailed Description
The MAX5855 is a high-performance, interpolating and modulating, 14-bit, 4.9Gsps RF DAC designed for DOCSIS 3.1/
3.0 remote PHY devices, CCAP, digital video broadcast modulators, point-to-point wireless, and instrumentation. The
device can synthesize up to 1GHz of instantaneous bandwidth at frequencies up to the Nyquist bandwidth (fDAC/2) of the
DAC. The major functional blocks of the device include a five-lane JESD204B interface which accepts 16-bit input data,
interpolation filters, a digital quadrature modulator and NCO, clock multiplying PLL + VCO and a 14-bit, 4.9Gsps RF DAC
core. The supporting functional blocks include the clock distribution system, reference system, and SPI interface. See
the detailed Functional Diagram.
The 16-bit input data enhances the accuracy of the interpolation and modulation functions and ensures true 14-bit data
is presented to the RF DAC core. The 16-bit input baseband data is supplied to the device using a five lane JESD204B
(DP[4:0]/DN[4:0]) interface operating at 9.8304Gbps.
The five-lane JESD204B interface has the following major components:
● A high-speed input receiver (Rx) consisting of a physical (PHY) layer for each of the five lanes and a common clock
multiplier unit (CMU). The PHY layer contains a variable gain amplifier (VGA) which receives the incoming signal and
decision feedback equalizer (DFE) to suppress inter-symbol interference. The PHY layer also includes a clock and
data recovery (CDR) unit to latch the incoming single-bit data and a de-serializer (DEMUX) to convert the data to a
20-bit parallel data bus.
● A receiver link layer (Rx Link) takes the 20 bits from the PHY and restores the 16-bit DAC data for each of the I and
Q channels. The Rx link consists of five Rx lanes, five Rx FIFOs, a Rx mapper and a Rx controller. The five Rx lanes
perform code group synchronization, 8b/10b decoding, frame synchronization and monitoring, interlane alignment and
monitoring, character replacement, and optional descrambling. The five lanes are fed into Rx FIFOs where data is
aligned by the Rx controller. Using the Rx mapper, data from each physical channel is mapped to a logical channel.
The DSP path consists of 4x linear phase interpolation filters for each of the I and Q channels. Interpolation reduces the
required input data rate to the device, relaxing the requirements on the FPGA or ASIC. In addition, interpolation increases
the separation between the desired signal and its aliased image easing filter design requirements.
After passing through the 4x interpolation stage, the complex signal is modulated using the LO signal generated by the
NCO and the digital quadrature modulator. The NCO allows for fully agile modulation of the input baseband signal for
direct RF synthesis with 32 bits of frequency-setting resolution. Placing the modulator at the output of the interpolator
chain allows for fully agile placement of the output carrier frequency within the Nyquist band of the DAC. The quadrature
modulator produces a real signal at its output, which is fed into the 14-bit DAC core where it is converted to an analog
RF signal. The analog output produces a full-scale current between 10mA and 40mA, driving 50Ω differential loads.
The clock distribution system provides a low-noise differential input buffer for the external master DAC clock (CLKP/
CLKN) and delivers all the necessary clocks to the internal blocks. The master DAC clock input accepts a differential sine-
wave or square-wave signal. A clock multiplying PLL and VCO is used to internally generate the 4915.2MHz sampling
clock using reference frequencies of 245.76MHz, 491.52MHz or 983.04MHz. The device provides a divided reference
clock (RCLKP/RCLKN) to ensure synchronization between the data source (FPGA or ASIC) and the DAC. The SYNCN
output can be used for error reporting from the DAC to the data source.
The reference system delivers the reference current to the DAC current source array and all bias currents necessary
for circuit operation. The reference system also includes a bypassable band-gap reference, which can be used as a
reference for the DAC full-scale current.
The SPI port is a bidirectional interface used for reading and writing status and control registers to configure the device.
The device operates from 1.0V and 1.8V power-supply voltages and consumes 2.7W at 4.9Gsps.
16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
Maxim Integrated | 21

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