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MAX5855 Datasheet(PDF) 85 Page - Maxim Integrated Products

Part No. MAX5855
Description  16-Bit, 4.9Gsps Wideband Interpolating and Modulating RF DAC with JESD204B Interface
Download  128 Pages
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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MAX5855 Datasheet(HTML) 85 Page - Maxim Integrated Products

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BIT
15
14
13
12
11
10
9
8
Field
SErrC
Reset
0x0
Access
Type
Write, Read
BIT
7
6
5
4
3
2
1
0
Field
BitSwap
AsyncAvl
rclk
Reset
0x0
0x0
0x1
Access
Type
Write, Read
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
SCtrl
22:21
ILA sequence detection control
0: ILA sequence detection is enabled
1: ILA sequence detection is disabled for the first
CfgRLinkMFrame.SNum frames
2: ILA sequence detection is disabled
DFSync
20
ILA restart on frame resynchronization control
0: Enable ILA restart on frame resynchronization
1: Disable ILA restart on frame resynchronization
SErrC
8
SYNC~ assert/deassert cycle control
0: SYNC~ error reporting assertion/deassertion per
JESD204B
1: Enable SYNC~ error reporting assertion/
deassertion on any frame - JESD204A
BitSwap
3
Bit Swap control
0: Disable Bit Swap MSB<–>LSB within an octet of
the Lane data
1: Enable Bit Swap MSB<–>LSB within an octet of
the Lane data
AsyncAvl
1
Initial Frame Synchronization state machine
control
0: Intial Frame Synchronization state machine
includes the FS_CHECK state
1: Intial Frame Synchronization state machine
bypasses the FS_CHECK state
rclk
0
Frame/sample clock source
0: Divided down Device Clock is used as frame/
sample clock
1: Frame clock
input from DAC/DSP is used as
frame/sample clock when the Device Clock is
not available
CfgRLinkMFrame (0x414)
Configure Multiframe control
BIT
31
30
29
28
27
26
25
24
Field
SNum[8:7]
Reset
0x3
Access
Type
Write, Read
MAX5855
16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com
Maxim Integrated | 85


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